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Fri, 12 Apr 2024 06:05:56 -0700 Received: from drhqmail201.nvidia.com (10.126.190.180) by drhqmail201.nvidia.com (10.126.190.180) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_256_GCM_SHA384) id 15.2.1544.4; Fri, 12 Apr 2024 06:05:56 -0700 Received: from sumitg-l4t.nvidia.com (10.127.8.10) by mail.nvidia.com (10.126.190.180) with Microsoft SMTP Server id 15.2.1544.4 via Frontend Transport; Fri, 12 Apr 2024 06:05:53 -0700 From: Sumit Gupta To: , , , , , , CC: , , , , , Subject: [Patch v3 1/2] dt-bindings: make sid and broadcast reg optional Date: Fri, 12 Apr 2024 18:35:39 +0530 Message-ID: <20240412130540.28447-2-sumitg@nvidia.com> X-Mailer: git-send-email 2.17.1 In-Reply-To: <20240412130540.28447-1-sumitg@nvidia.com> References: <20240412130540.28447-1-sumitg@nvidia.com> X-NVConfidentiality: public Precedence: bulk X-Mailing-List: linux-tegra@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 X-NV-OnPremToCloud: ExternallySecured X-EOPAttributedMessage: 0 X-MS-PublicTrafficType: Email X-MS-TrafficTypeDiagnostic: SA2PEPF00001505:EE_|DS7PR12MB5933:EE_ X-MS-Office365-Filtering-Correlation-Id: aed766e2-a69f-4ced-bcb3-08dc5af1524b X-MS-Exchange-SenderADCheck: 1 X-MS-Exchange-AntiSpam-Relay: 0 X-Microsoft-Antispam: BCL:0; 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X-OriginatorOrg: Nvidia.com X-MS-Exchange-CrossTenant-OriginalArrivalTime: 12 Apr 2024 13:06:09.2831 (UTC) X-MS-Exchange-CrossTenant-Network-Message-Id: aed766e2-a69f-4ced-bcb3-08dc5af1524b X-MS-Exchange-CrossTenant-Id: 43083d15-7273-40c1-b7db-39efd9ccc17a X-MS-Exchange-CrossTenant-OriginalAttributedTenantConnectingIp: TenantId=43083d15-7273-40c1-b7db-39efd9ccc17a;Ip=[216.228.118.233];Helo=[mail.nvidia.com] X-MS-Exchange-CrossTenant-AuthSource: SA2PEPF00001505.namprd04.prod.outlook.com X-MS-Exchange-CrossTenant-AuthAs: Anonymous X-MS-Exchange-CrossTenant-FromEntityHeader: HybridOnPrem X-MS-Exchange-Transport-CrossTenantHeadersStamped: DS7PR12MB5933 MC SID and Broadbast channel register access is restricted for Guest VM. Make both the regions as optional for SoC's from Tegra186 onwards. Tegra MC driver will skip access to the restricted registers from Guest if the respective regions are not present in the memory-controller node of Guest DT. Suggested-by: Thierry Reding Signed-off-by: Sumit Gupta --- .../nvidia,tegra186-mc.yaml | 95 ++++++++++--------- 1 file changed, 49 insertions(+), 46 deletions(-) diff --git a/Documentation/devicetree/bindings/memory-controllers/nvidia,tegra186-mc.yaml b/Documentation/devicetree/bindings/memory-controllers/nvidia,tegra186-mc.yaml index 935d63d181d9..e0bd013ecca3 100644 --- a/Documentation/devicetree/bindings/memory-controllers/nvidia,tegra186-mc.yaml +++ b/Documentation/devicetree/bindings/memory-controllers/nvidia,tegra186-mc.yaml @@ -34,11 +34,11 @@ properties: - nvidia,tegra234-mc reg: - minItems: 6 + minItems: 4 maxItems: 18 reg-names: - minItems: 6 + minItems: 4 maxItems: 18 interrupts: @@ -151,12 +151,13 @@ allOf: reg-names: items: - - const: sid - - const: broadcast - - const: ch0 - - const: ch1 - - const: ch2 - - const: ch3 + enum: + - sid + - broadcast + - ch0 + - ch1 + - ch2 + - ch3 - if: properties: @@ -165,29 +166,30 @@ allOf: then: properties: reg: - minItems: 18 + minItems: 16 description: 17 memory controller channels and 1 for stream-id registers reg-names: items: - - const: sid - - const: broadcast - - const: ch0 - - const: ch1 - - const: ch2 - - const: ch3 - - const: ch4 - - const: ch5 - - const: ch6 - - const: ch7 - - const: ch8 - - const: ch9 - - const: ch10 - - const: ch11 - - const: ch12 - - const: ch13 - - const: ch14 - - const: ch15 + enum: + - sid + - broadcast + - ch0 + - ch1 + - ch2 + - ch3 + - ch4 + - ch5 + - ch6 + - ch7 + - ch8 + - ch9 + - ch10 + - ch11 + - ch12 + - ch13 + - ch14 + - ch15 - if: properties: @@ -196,29 +198,30 @@ allOf: then: properties: reg: - minItems: 18 + minItems: 16 description: 17 memory controller channels and 1 for stream-id registers reg-names: items: - - const: sid - - const: broadcast - - const: ch0 - - const: ch1 - - const: ch2 - - const: ch3 - - const: ch4 - - const: ch5 - - const: ch6 - - const: ch7 - - const: ch8 - - const: ch9 - - const: ch10 - - const: ch11 - - const: ch12 - - const: ch13 - - const: ch14 - - const: ch15 + enum: + - sid + - broadcast + - ch0 + - ch1 + - ch2 + - ch3 + - ch4 + - ch5 + - ch6 + - ch7 + - ch8 + - ch9 + - ch10 + - ch11 + - ch12 + - ch13 + - ch14 + - ch15 additionalProperties: false