From patchwork Thu Dec 29 13:32:03 2022 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Luca Ceresoli X-Patchwork-Id: 1720072 Return-Path: X-Original-To: incoming@patchwork.ozlabs.org Delivered-To: patchwork-incoming@legolas.ozlabs.org Authentication-Results: legolas.ozlabs.org; spf=pass (sender SPF authorized) smtp.mailfrom=vger.kernel.org (client-ip=2620:137:e000::1:20; helo=out1.vger.email; envelope-from=linux-tegra-owner@vger.kernel.org; receiver=) Authentication-Results: legolas.ozlabs.org; dkim=pass (2048-bit key; unprotected) header.d=bootlin.com header.i=@bootlin.com header.a=rsa-sha256 header.s=gm1 header.b=IcrYx/bg; dkim-atps=neutral Received: from out1.vger.email (out1.vger.email [IPv6:2620:137:e000::1:20]) by legolas.ozlabs.org (Postfix) with ESMTP id 4NjTrY6XHXz23dD for ; Fri, 30 Dec 2022 00:34:21 +1100 (AEDT) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S233634AbiL2NeO (ORCPT ); Thu, 29 Dec 2022 08:34:14 -0500 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:53476 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S233564AbiL2Ndo (ORCPT ); Thu, 29 Dec 2022 08:33:44 -0500 Received: from relay9-d.mail.gandi.net (relay9-d.mail.gandi.net [217.70.183.199]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id 645C512755; Thu, 29 Dec 2022 05:33:06 -0800 (PST) Received: from booty.fritz.box (unknown [77.244.183.192]) (Authenticated sender: luca.ceresoli@bootlin.com) by mail.gandi.net (Postfix) with ESMTPA id DEB21FF80E; Thu, 29 Dec 2022 13:33:02 +0000 (UTC) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=bootlin.com; s=gm1; t=1672320785; h=from:from:reply-to:subject:subject:date:date:message-id:message-id: to:to:cc:cc:mime-version:mime-version: content-transfer-encoding:content-transfer-encoding: in-reply-to:in-reply-to:references:references; bh=CW64MxchVb9saBnb7wZiFjtE7xT/bCq9uwLuPiV613I=; b=IcrYx/bguyUZYs+cfdCWOZKBpYj9tOyR/uyKoCnbhNn511p6uce8S6pEgH79ipOpwfdfWI PULqa9PHCX62Fy380xq/DcIFGNRnTVbtSM6eUOo10mhqBbycLGIzlmSkzc8Lh7oAqR6IRy fKKsxQ/XagTMVei/I0VjseCFLdV+7jlTZ5khTRvW9KtIjgZqcAqztSyLbB9D4jEMz0BZ5X PIbSqyF33yvcg4cwZ/z5H5r7IhitRZRDUisxuYFXFoD9MPBJH7qGOUUpHmjXYv5218Yars j4B8lo9DAnixhULyqLbMQ67b3d3nV2pfFkIE010b9Pk/tO9kGoIdDWQYy+7J6Q== From: Luca Ceresoli To: Thierry Reding , Jonathan Hunter , Sowjanya Komatineni , Luca Ceresoli , David Airlie , Daniel Vetter , Rob Herring , Krzysztof Kozlowski , Mauro Carvalho Chehab , Greg Kroah-Hartman , Dmitry Osipenko , Hans Verkuil Cc: linux-media@vger.kernel.org, linux-tegra@vger.kernel.org, dri-devel@lists.freedesktop.org, devicetree@vger.kernel.org, linux-kernel@vger.kernel.org, linux-staging@lists.linux.dev, Thomas Petazzoni , Paul Kocialkowski , Richard Leitner Subject: [PATCH v3 19/21] staging: media: tegra-video: add hooks for planar YUV and H/V flip Date: Thu, 29 Dec 2022 14:32:03 +0100 Message-Id: <20221229133205.981397-20-luca.ceresoli@bootlin.com> X-Mailer: git-send-email 2.34.1 In-Reply-To: <20221229133205.981397-1-luca.ceresoli@bootlin.com> References: <20221229133205.981397-1-luca.ceresoli@bootlin.com> MIME-Version: 1.0 X-Spam-Status: No, score=-2.8 required=5.0 tests=BAYES_00,DKIM_SIGNED, DKIM_VALID,DKIM_VALID_AU,DKIM_VALID_EF,RCVD_IN_DNSWL_LOW, RCVD_IN_MSPIKE_H2,SPF_HELO_NONE,SPF_PASS autolearn=ham autolearn_force=no version=3.4.6 X-Spam-Checker-Version: SpamAssassin 3.4.6 (2021-04-09) on lindbergh.monkeyblade.net Precedence: bulk List-ID: X-Mailing-List: linux-tegra@vger.kernel.org Tegra20 supports planar YUV422 capture, which can be implemented by writing U and V base address registers in addition to the "main" base buffer address register. It also supports H and V flip, which among others requires to write the start address (i.e. the 1st offset to write, at the end of the buffer or line) in more registers for Y and, for planar formats, U and V. Add minimal hooks in VI to allow per-SoC optional support to those features: - variables in struct tegra_vi for the U and V buffer base offsets - variables in struct tegra_vi for the Y, U and V buffer start offsets - an optional per-soc VI operation to compute those values on queue setup Signed-off-by: Luca Ceresoli --- No changes in v3 No changes in v2 --- drivers/staging/media/tegra-video/vi.c | 4 ++++ drivers/staging/media/tegra-video/vi.h | 14 ++++++++++++++ 2 files changed, 18 insertions(+) diff --git a/drivers/staging/media/tegra-video/vi.c b/drivers/staging/media/tegra-video/vi.c index 760606c65a97..4a066b61ab8e 100644 --- a/drivers/staging/media/tegra-video/vi.c +++ b/drivers/staging/media/tegra-video/vi.c @@ -92,6 +92,7 @@ tegra_get_format_by_fourcc(struct tegra_vi *vi, u32 fourcc) /* * videobuf2 queue operations */ + static int tegra_channel_queue_setup(struct vb2_queue *vq, unsigned int *nbuffers, unsigned int *nplanes, @@ -107,6 +108,9 @@ static int tegra_channel_queue_setup(struct vb2_queue *vq, sizes[0] = chan->format.sizeimage; alloc_devs[0] = chan->vi->dev; + if (chan->vi->ops->channel_queue_setup) + chan->vi->ops->channel_queue_setup(chan); + return 0; } diff --git a/drivers/staging/media/tegra-video/vi.h b/drivers/staging/media/tegra-video/vi.h index d5e1ed4217e0..0503eb678556 100644 --- a/drivers/staging/media/tegra-video/vi.h +++ b/drivers/staging/media/tegra-video/vi.h @@ -47,6 +47,7 @@ struct tegra_vi_channel; * @channel_host1x_syncpt_free: free all synchronization points * @vi_fmt_align: modify `pix` to fit the hardware alignment * requirements and fill image geometry + * @channel_queue_setup: additional operations at the end of vb2_ops::queue_setup * @vi_start_streaming: starts media pipeline, subdevice streaming, sets up * VI for capture and runs capture start and capture finish * kthreads for capturing frames to buffer and returns them back. @@ -58,6 +59,7 @@ struct tegra_vi_ops { int (*channel_host1x_syncpt_init)(struct tegra_vi_channel *chan); void (*channel_host1x_syncpt_free)(struct tegra_vi_channel *chan); void (*vi_fmt_align)(struct v4l2_pix_format *pix, unsigned int bpp); + void (*channel_queue_setup)(struct tegra_vi_channel *chan); int (*vi_start_streaming)(struct vb2_queue *vq, u32 count); void (*vi_stop_streaming)(struct vb2_queue *vq); }; @@ -148,6 +150,12 @@ struct tegra_vi { * @queue: vb2 buffers queue * @sequence: V4L2 buffers sequence number * + * @addr_offset_u: U plane base address, relative to buffer base address (only for planar) + * @addr_offset_v: V plane base address, relative to buffer base address (only for planar) + * @start_offset: 1st Y byte to write, relative to buffer base address (for H/V flip) + * @start_offset_u: 1st U byte to write, relative to buffer base address (for H/V flip) + * @start_offset_v: 1st V byte to write, relative to buffer base address (for H/V flip) + * * @capture: list of queued buffers for capture * @start_lock: protects the capture queued list * @done: list of capture done queued buffers @@ -187,6 +195,12 @@ struct tegra_vi_channel { struct vb2_queue queue; u32 sequence; + unsigned int addr_offset_u; + unsigned int addr_offset_v; + unsigned int start_offset; + unsigned int start_offset_u; + unsigned int start_offset_v; + struct list_head capture; /* protects the capture queued list */ spinlock_t start_lock;