diff mbox series

PCI: tegra194: Remove unnecessary MSI enable reg save and restore

Message ID 20211226074910.2722-1-jszhang@kernel.org
State Not Applicable
Headers show
Series PCI: tegra194: Remove unnecessary MSI enable reg save and restore | expand

Commit Message

Jisheng Zhang Dec. 26, 2021, 7:49 a.m. UTC
The integrated MSI Receiver enable register is always initialized in
dw_pcie_setup_rc() which is also called in resume code path, so we
don't need to save/restore the enable register during suspend/resume.

Signed-off-by: Jisheng Zhang <jszhang@kernel.org>
---
 drivers/pci/controller/dwc/pcie-tegra194.c | 9 ---------
 1 file changed, 9 deletions(-)

Comments

Lorenzo Pieralisi April 8, 2022, 11:56 a.m. UTC | #1
[+cc Vidya]

On Sun, Dec 26, 2021 at 03:49:10PM +0800, Jisheng Zhang wrote:
> The integrated MSI Receiver enable register is always initialized in
> dw_pcie_setup_rc() which is also called in resume code path, so we
> don't need to save/restore the enable register during suspend/resume.
> 
> Signed-off-by: Jisheng Zhang <jszhang@kernel.org>
> ---
>  drivers/pci/controller/dwc/pcie-tegra194.c | 9 ---------
>  1 file changed, 9 deletions(-)

Need an ACK from Nvidia folks.

Lorenzo

> diff --git a/drivers/pci/controller/dwc/pcie-tegra194.c b/drivers/pci/controller/dwc/pcie-tegra194.c
> index 904976913081..678898985319 100644
> --- a/drivers/pci/controller/dwc/pcie-tegra194.c
> +++ b/drivers/pci/controller/dwc/pcie-tegra194.c
> @@ -186,8 +186,6 @@
>  #define N_FTS_VAL					52
>  #define FTS_VAL						52
>  
> -#define PORT_LOGIC_MSI_CTRL_INT_0_EN		0x828
> -
>  #define GEN3_EQ_CONTROL_OFF			0x8a8
>  #define GEN3_EQ_CONTROL_OFF_PSET_REQ_VEC_SHIFT	8
>  #define GEN3_EQ_CONTROL_OFF_PSET_REQ_VEC_MASK	GENMASK(23, 8)
> @@ -2189,9 +2187,6 @@ static int tegra_pcie_dw_suspend_noirq(struct device *dev)
>  	if (!pcie->link_state)
>  		return 0;
>  
> -	/* Save MSI interrupt vector */
> -	pcie->msi_ctrl_int = dw_pcie_readl_dbi(&pcie->pci,
> -					       PORT_LOGIC_MSI_CTRL_INT_0_EN);
>  	tegra_pcie_downstream_dev_to_D0(pcie);
>  	tegra_pcie_dw_pme_turnoff(pcie);
>  	tegra_pcie_unconfig_controller(pcie);
> @@ -2223,10 +2218,6 @@ static int tegra_pcie_dw_resume_noirq(struct device *dev)
>  	if (ret < 0)
>  		goto fail_host_init;
>  
> -	/* Restore MSI interrupt vector */
> -	dw_pcie_writel_dbi(&pcie->pci, PORT_LOGIC_MSI_CTRL_INT_0_EN,
> -			   pcie->msi_ctrl_int);
> -
>  	return 0;
>  
>  fail_host_init:
> -- 
> 2.34.1
>
Vidya Sagar April 11, 2022, 11:33 a.m. UTC | #2
On 4/8/2022 5:26 PM, Lorenzo Pieralisi wrote:
> External email: Use caution opening links or attachments
> 
> 
> [+cc Vidya]
> 
> On Sun, Dec 26, 2021 at 03:49:10PM +0800, Jisheng Zhang wrote:
>> The integrated MSI Receiver enable register is always initialized in
>> dw_pcie_setup_rc() which is also called in resume code path, so we
>> don't need to save/restore the enable register during suspend/resume.
>>
>> Signed-off-by: Jisheng Zhang <jszhang@kernel.org>
>> ---
>>   drivers/pci/controller/dwc/pcie-tegra194.c | 9 ---------
>>   1 file changed, 9 deletions(-)
> 
> Need an ACK from Nvidia folks.

Looks good to me.
I couldn't verify it on Nvidia platform as we are facing some issue with 
suspend/resume sequence.
I'll verify and update as soon as I could get suspend/resume working.

Acked-by: Vidya Sagar <vidyas@nvidia.com>

- Vidya Sagar
> 
> Lorenzo
> 
>> diff --git a/drivers/pci/controller/dwc/pcie-tegra194.c b/drivers/pci/controller/dwc/pcie-tegra194.c
>> index 904976913081..678898985319 100644
>> --- a/drivers/pci/controller/dwc/pcie-tegra194.c
>> +++ b/drivers/pci/controller/dwc/pcie-tegra194.c
>> @@ -186,8 +186,6 @@
>>   #define N_FTS_VAL                                    52
>>   #define FTS_VAL                                              52
>>
>> -#define PORT_LOGIC_MSI_CTRL_INT_0_EN         0x828
>> -
>>   #define GEN3_EQ_CONTROL_OFF                  0x8a8
>>   #define GEN3_EQ_CONTROL_OFF_PSET_REQ_VEC_SHIFT       8
>>   #define GEN3_EQ_CONTROL_OFF_PSET_REQ_VEC_MASK        GENMASK(23, 8)
>> @@ -2189,9 +2187,6 @@ static int tegra_pcie_dw_suspend_noirq(struct device *dev)
>>        if (!pcie->link_state)
>>                return 0;
>>
>> -     /* Save MSI interrupt vector */
>> -     pcie->msi_ctrl_int = dw_pcie_readl_dbi(&pcie->pci,
>> -                                            PORT_LOGIC_MSI_CTRL_INT_0_EN);
>>        tegra_pcie_downstream_dev_to_D0(pcie);
>>        tegra_pcie_dw_pme_turnoff(pcie);
>>        tegra_pcie_unconfig_controller(pcie);
>> @@ -2223,10 +2218,6 @@ static int tegra_pcie_dw_resume_noirq(struct device *dev)
>>        if (ret < 0)
>>                goto fail_host_init;
>>
>> -     /* Restore MSI interrupt vector */
>> -     dw_pcie_writel_dbi(&pcie->pci, PORT_LOGIC_MSI_CTRL_INT_0_EN,
>> -                        pcie->msi_ctrl_int);
>> -
>>        return 0;
>>
>>   fail_host_init:
>> --
>> 2.34.1
>>
Lorenzo Pieralisi April 11, 2022, 1 p.m. UTC | #3
On Sun, 26 Dec 2021 15:49:10 +0800, Jisheng Zhang wrote:
> The integrated MSI Receiver enable register is always initialized in
> dw_pcie_setup_rc() which is also called in resume code path, so we
> don't need to save/restore the enable register during suspend/resume.
> 
> 

Applied to pci/dwc, thanks!

[1/1] PCI: tegra194: Remove unnecessary MSI enable reg save and restore
      https://git.kernel.org/lpieralisi/pci/c/571dda6ca5

Thanks,
Lorenzo
diff mbox series

Patch

diff --git a/drivers/pci/controller/dwc/pcie-tegra194.c b/drivers/pci/controller/dwc/pcie-tegra194.c
index 904976913081..678898985319 100644
--- a/drivers/pci/controller/dwc/pcie-tegra194.c
+++ b/drivers/pci/controller/dwc/pcie-tegra194.c
@@ -186,8 +186,6 @@ 
 #define N_FTS_VAL					52
 #define FTS_VAL						52
 
-#define PORT_LOGIC_MSI_CTRL_INT_0_EN		0x828
-
 #define GEN3_EQ_CONTROL_OFF			0x8a8
 #define GEN3_EQ_CONTROL_OFF_PSET_REQ_VEC_SHIFT	8
 #define GEN3_EQ_CONTROL_OFF_PSET_REQ_VEC_MASK	GENMASK(23, 8)
@@ -2189,9 +2187,6 @@  static int tegra_pcie_dw_suspend_noirq(struct device *dev)
 	if (!pcie->link_state)
 		return 0;
 
-	/* Save MSI interrupt vector */
-	pcie->msi_ctrl_int = dw_pcie_readl_dbi(&pcie->pci,
-					       PORT_LOGIC_MSI_CTRL_INT_0_EN);
 	tegra_pcie_downstream_dev_to_D0(pcie);
 	tegra_pcie_dw_pme_turnoff(pcie);
 	tegra_pcie_unconfig_controller(pcie);
@@ -2223,10 +2218,6 @@  static int tegra_pcie_dw_resume_noirq(struct device *dev)
 	if (ret < 0)
 		goto fail_host_init;
 
-	/* Restore MSI interrupt vector */
-	dw_pcie_writel_dbi(&pcie->pci, PORT_LOGIC_MSI_CTRL_INT_0_EN,
-			   pcie->msi_ctrl_int);
-
 	return 0;
 
 fail_host_init: