| Message ID | 20211217165919.2700920-3-thierry.reding@gmail.com |
|---|---|
| State | Changes Requested |
| Headers | show |
| Series | [1/5] dt-bindings: memory: Document Tegra210 EMC table | expand |
On 17/12/2021 17:59, Thierry Reding wrote: > From: Thierry Reding <treding@nvidia.com> > > Document the bindings for the memory controller found on Tegra114 SoCs. > > Signed-off-by: Thierry Reding <treding@nvidia.com> > --- > .../nvidia,tegra114-mc.yaml | 85 +++++++++++++++++++ > 1 file changed, 85 insertions(+) > create mode 100644 Documentation/devicetree/bindings/memory-controllers/nvidia,tegra114-mc.yaml > > diff --git a/Documentation/devicetree/bindings/memory-controllers/nvidia,tegra114-mc.yaml b/Documentation/devicetree/bindings/memory-controllers/nvidia,tegra114-mc.yaml > new file mode 100644 > index 000000000000..2fa50eb3aadb > --- /dev/null > +++ b/Documentation/devicetree/bindings/memory-controllers/nvidia,tegra114-mc.yaml > @@ -0,0 +1,85 @@ > +# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) > +%YAML 1.2 > +--- > +$id: http://devicetree.org/schemas/memory-controllers/nvidia,tegra114-mc.yaml# > +$schema: http://devicetree.org/meta-schemas/core.yaml# > + > +title: NVIDIA Tegra114 SoC Memory Controller > + > +maintainers: > + - Thierry Reding <thierry.reding@gmail.com> > + - Jon Hunter <jonathanh@nvidia.com> > + > +description: | > + The Tegra114 Memory Controller architecturally consists of the following parts: > + > + Arbitration Domains, which can handle a single request or response per > + clock from a group of clients. Typically, a system has a single Arbitration > + Domain, but an implementation may divide the client space into multiple > + Arbitration Domains to increase the effective system bandwidth. > + > + Protocol Arbiter, which manage a related pool of memory devices. A system > + may have a single Protocol Arbiter or multiple Protocol Arbiters. > + > + Memory Crossbar, which routes request and responses between Arbitration > + Domains and Protocol Arbiters. In the simplest version of the system, the > + Memory Crossbar is just a pass through between a single Arbitration Domain > + and a single Protocol Arbiter. > + > + Global Resources, which include things like configuration registers which > + are shared across the Memory Subsystem. > + > + The Tegra114 Memory Controller handles memory requests from internal clients > + and arbitrates among them to allocate memory bandwidth for DDR3L and LPDDR2 > + SDRAMs. > + > +properties: > + compatible: > + const: nvidia,tegra114-mc > + > + reg: > + maxItems: 1 > + > + clocks: > + maxItems: 1 > + > + clock-names: > + items: > + - const: mc > + > + interrupts: > + maxItems: 1 > + > + "#reset-cells": > + const: 1 > + > + "#iommu-cells": > + const: 1 > + > +required: > + - compatible > + - reg > + - interrupts > + - clocks > + - clock-names > + - "#reset-cells" > + - "#iommu-cells" > + > +additionalProperties: false The binding looks the same as Tegra210, Tegra 20 MC. What is the point of having three separate binding documents which are exactly the same? Best regards, Krzysztof
On Fri, 17 Dec 2021 17:59:17 +0100, Thierry Reding wrote: > From: Thierry Reding <treding@nvidia.com> > > Document the bindings for the memory controller found on Tegra114 SoCs. > > Signed-off-by: Thierry Reding <treding@nvidia.com> > --- > .../nvidia,tegra114-mc.yaml | 85 +++++++++++++++++++ > 1 file changed, 85 insertions(+) > create mode 100644 Documentation/devicetree/bindings/memory-controllers/nvidia,tegra114-mc.yaml > Running 'make dtbs_check' with the schema in this patch gives the following warnings. Consider if they are expected or the schema is incorrect. These may not be new warnings. Note that it is not yet a requirement to have 0 warnings for dtbs_check. This will change in the future. Full log is available here: https://patchwork.ozlabs.org/patch/1570202 memory-controller@70019000: '#reset-cells' is a required property arch/arm/boot/dts/tegra114-dalmore.dt.yaml arch/arm/boot/dts/tegra114-roth.dt.yaml arch/arm/boot/dts/tegra114-tn7.dt.yaml
diff --git a/Documentation/devicetree/bindings/memory-controllers/nvidia,tegra114-mc.yaml b/Documentation/devicetree/bindings/memory-controllers/nvidia,tegra114-mc.yaml new file mode 100644 index 000000000000..2fa50eb3aadb --- /dev/null +++ b/Documentation/devicetree/bindings/memory-controllers/nvidia,tegra114-mc.yaml @@ -0,0 +1,85 @@ +# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) +%YAML 1.2 +--- +$id: http://devicetree.org/schemas/memory-controllers/nvidia,tegra114-mc.yaml# +$schema: http://devicetree.org/meta-schemas/core.yaml# + +title: NVIDIA Tegra114 SoC Memory Controller + +maintainers: + - Thierry Reding <thierry.reding@gmail.com> + - Jon Hunter <jonathanh@nvidia.com> + +description: | + The Tegra114 Memory Controller architecturally consists of the following parts: + + Arbitration Domains, which can handle a single request or response per + clock from a group of clients. Typically, a system has a single Arbitration + Domain, but an implementation may divide the client space into multiple + Arbitration Domains to increase the effective system bandwidth. + + Protocol Arbiter, which manage a related pool of memory devices. A system + may have a single Protocol Arbiter or multiple Protocol Arbiters. + + Memory Crossbar, which routes request and responses between Arbitration + Domains and Protocol Arbiters. In the simplest version of the system, the + Memory Crossbar is just a pass through between a single Arbitration Domain + and a single Protocol Arbiter. + + Global Resources, which include things like configuration registers which + are shared across the Memory Subsystem. + + The Tegra114 Memory Controller handles memory requests from internal clients + and arbitrates among them to allocate memory bandwidth for DDR3L and LPDDR2 + SDRAMs. + +properties: + compatible: + const: nvidia,tegra114-mc + + reg: + maxItems: 1 + + clocks: + maxItems: 1 + + clock-names: + items: + - const: mc + + interrupts: + maxItems: 1 + + "#reset-cells": + const: 1 + + "#iommu-cells": + const: 1 + +required: + - compatible + - reg + - interrupts + - clocks + - clock-names + - "#reset-cells" + - "#iommu-cells" + +additionalProperties: false + +examples: + - | + #include <dt-bindings/clock/tegra114-car.h> + #include <dt-bindings/interrupt-controller/arm-gic.h> + + memory-controller@70019000 { + compatible = "nvidia,tegra114-mc"; + reg = <0x70019000 0x1000>; + interrupts = <GIC_SPI 77 IRQ_TYPE_LEVEL_HIGH>; + + clocks = <&tegra_car TEGRA114_CLK_MC>; + clock-names = "mc"; + + #reset-cells = <1>; + #iommu-cells = <1>; + };