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[3/3] arm64: tegra: Add "reg" property for TCU on Tegra194

Message ID 20210326174641.1612738-4-thierry.reding@gmail.com
State Rejected
Headers show
Series arm64: tegra: Add earlycon support on Tegra194 | expand

Commit Message

Thierry Reding March 26, 2021, 5:46 p.m. UTC 
From: Thierry Reding <treding@nvidia.com>

Technically the TCU doesn't have any registers but works with two
mailboxes that serve as RX and TX FIFOs. However, if used as early
console via /chosen/stdout-path, the earlycon code will want to use
the "reg" property to initialize the I/O memory base address that
will in turn be used to access the TX FIFO.

Add the "reg" property to the TCU device tree node to make earlycon
support work out of the box.

Signed-off-by: Thierry Reding <treding@nvidia.com>
---
 arch/arm64/boot/dts/nvidia/tegra194.dtsi | 4 +++-
 1 file changed, 3 insertions(+), 1 deletion(-)
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Patch

diff --git a/arch/arm64/boot/dts/nvidia/tegra194.dtsi b/arch/arm64/boot/dts/nvidia/tegra194.dtsi
index db68d53f5de0..f9fc481f90c7 100644
--- a/arch/arm64/boot/dts/nvidia/tegra194.dtsi
+++ b/arch/arm64/boot/dts/nvidia/tegra194.dtsi
@@ -2537,8 +2537,10 @@  sound {
 		assigned-clock-rates = <258000000>;
 	};
 
-	tcu: tcu {
+	tcu: tcu@c168000 {
 		compatible = "nvidia,tegra194-tcu";
+		/* TX mailbox for use with earlycon */
+		reg = <0x0 0x0c168000 0x0 0x4>;
 		mboxes = <&hsp_top0 TEGRA_HSP_MBOX_TYPE_SM TEGRA_HSP_SM_RX(0)>,
 		         <&hsp_aon TEGRA_HSP_MBOX_TYPE_SM TEGRA_HSP_SM_TX(1)>;
 		mbox-names = "rx", "tx";