From patchwork Wed Jan 23 09:39:50 2019 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Thierry Reding X-Patchwork-Id: 1029817 Return-Path: X-Original-To: incoming@patchwork.ozlabs.org Delivered-To: patchwork-incoming@bilbo.ozlabs.org Authentication-Results: ozlabs.org; spf=none (mailfrom) smtp.mailfrom=vger.kernel.org (client-ip=209.132.180.67; helo=vger.kernel.org; envelope-from=linux-tegra-owner@vger.kernel.org; receiver=) Authentication-Results: ozlabs.org; dmarc=pass (p=none dis=none) header.from=gmail.com Authentication-Results: ozlabs.org; dkim=pass (2048-bit key; unprotected) header.d=gmail.com header.i=@gmail.com header.b="Bsg7dHCl"; dkim-atps=neutral Received: from vger.kernel.org (vger.kernel.org [209.132.180.67]) by ozlabs.org (Postfix) with ESMTP id 43l0cy5xf4z9s9G for ; Wed, 23 Jan 2019 20:40:02 +1100 (AEDT) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1727266AbfAWJkC (ORCPT ); Wed, 23 Jan 2019 04:40:02 -0500 Received: from mail-wm1-f65.google.com ([209.85.128.65]:55211 "EHLO mail-wm1-f65.google.com" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1726207AbfAWJkC (ORCPT ); Wed, 23 Jan 2019 04:40:02 -0500 Received: by mail-wm1-f65.google.com with SMTP id a62so1269017wmh.4 for ; Wed, 23 Jan 2019 01:40:00 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=gmail.com; s=20161025; h=from:to:cc:subject:date:message-id:in-reply-to:references :mime-version:content-transfer-encoding; bh=cUH3hZoO0g/LZ+pZUMo8PX/7722b7rvBvBxyOPDoCcc=; b=Bsg7dHClEumIlK7NQ90RfSh3oKFnQjzi1DpXim7CEZogTl5jO7wEb4YvkHIYiXncOp p5Yclo1Yy2UL/5hPGOuTOPMIYfmvB8l9bMJVgNsLyheh9qmrfPW8TS/stGYbCrksG66u wG3dzQpWNDd6BXBqVX27RRI4mWWbXRcSHJCpDFXqBKu5P1qtoWVfT+GqU0zQr+wESClw 9KVsGP/ScNWGfKYik2WM2yZChoU7Ui2qBU3gYm/2ye0HF0Q2OPXOnUJKWjA633TjgTeO Ns+d/ctJB0GlRzc+BnPmO1Th6Ug24ptAT98od76gG2K4RDxROkSbQLKdEuSrG4l9GjfM WZGQ== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:from:to:cc:subject:date:message-id:in-reply-to :references:mime-version:content-transfer-encoding; bh=cUH3hZoO0g/LZ+pZUMo8PX/7722b7rvBvBxyOPDoCcc=; b=HuPxiGEBUmkORyPv0nbcAs4ybQiRyvqbGWboVGajL8eb/HzIQlrg8Rg3ewvVh5bC5n ceaBQLd9J9Vo4HODgV0Z+yq2VqFCjrjZt+SIWWw2fH1oAwKUaIBH/cfolrkTI/mXCtOq ssvXz2Z5Ohif3zkmlxZn7VB3qL9mG2wbl3NUkvaj/p6ZGnEZNnRkNoERNJrRO+r65rDE G5e5sAo20p0LcdkL8UmSt5Ia2+24QHvTrtjW26Y5b1WOpJ3DCGf+FPrAB7zglqEdU4Fn 2uh24z3q30vr3FsFBLWDdzDLsR7pROAG0LgWbOOfRZTDJ3R6V6HkgXN2v1WJAfIW6UCu EBaQ== X-Gm-Message-State: AJcUukfxUyqhZjwmRnrxq5SX8s6UiXIGnIDSewBaCe2e+q/+zA6/mqj8 tVwTVWUyF0Zlzdml1gW1yUQ= X-Google-Smtp-Source: ALg8bN7yzEsHes0VDsRw07KZi9RcP9Vz+FDVPEv5AkJ3TLD9sYzAr9A67oX0STPfjCYHGdOHtHmNig== X-Received: by 2002:a1c:5a42:: with SMTP id o63mr1957199wmb.88.1548236399590; Wed, 23 Jan 2019 01:39:59 -0800 (PST) Received: from localhost (pD9E51040.dip0.t-ipconnect.de. [217.229.16.64]) by smtp.gmail.com with ESMTPSA id x20sm77813081wme.6.2019.01.23.01.39.58 (version=TLS1_2 cipher=ECDHE-RSA-CHACHA20-POLY1305 bits=256/256); Wed, 23 Jan 2019 01:39:58 -0800 (PST) From: Thierry Reding To: Thierry Reding Cc: Mikko Perttunen , Dmitry Osipenko , dri-devel@lists.freedesktop.org, linux-tegra@vger.kernel.org Subject: [PATCH 4/5] drm/tegra: Restrict IOVA space to DMA mask Date: Wed, 23 Jan 2019 10:39:50 +0100 Message-Id: <20190123093951.24908-5-thierry.reding@gmail.com> X-Mailer: git-send-email 2.19.1 In-Reply-To: <20190123093951.24908-1-thierry.reding@gmail.com> References: <20190123093951.24908-1-thierry.reding@gmail.com> MIME-Version: 1.0 Sender: linux-tegra-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: linux-tegra@vger.kernel.org From: Thierry Reding On Tegra186 and later, the ARM SMMU provides an input address space that is 48 bits wide. However, memory clients can only address up to 40 bits. If the geometry is used as-is, allocations of IOVA space can end up in a region that cannot be addressed by the memory clients. To fix this, restrict the IOVA space to the DMA mask of the host1x device. Note that, technically, the IOVA space needs to be restricted to the intersection of the DMA masks for all clients that are attached to the IOMMU domain. In practice using the DMA mask of the host1x device is sufficient because all host1x clients share the same DMA mask. Signed-off-by: Thierry Reding --- drivers/gpu/drm/tegra/drm.c | 5 +++-- 1 file changed, 3 insertions(+), 2 deletions(-) diff --git a/drivers/gpu/drm/tegra/drm.c b/drivers/gpu/drm/tegra/drm.c index 271c7a5fc954..0c5f1e6a0446 100644 --- a/drivers/gpu/drm/tegra/drm.c +++ b/drivers/gpu/drm/tegra/drm.c @@ -136,11 +136,12 @@ static int tegra_drm_load(struct drm_device *drm, unsigned long flags) if (tegra->domain) { u64 carveout_start, carveout_end, gem_start, gem_end; + u64 dma_mask = dma_get_mask(&device->dev); dma_addr_t start, end; unsigned long order; - start = tegra->domain->geometry.aperture_start; - end = tegra->domain->geometry.aperture_end; + start = tegra->domain->geometry.aperture_start & dma_mask; + end = tegra->domain->geometry.aperture_end & dma_mask; gem_start = start; gem_end = end - CARVEOUT_SZ;