diff mbox series

[6/7] arm64: tegra: Add VIC support on Tegra194

Message ID 20181123123138.20739-6-thierry.reding@gmail.com
State Accepted
Headers show
Series [1/7] gpu: host1x: Resize channel register region on Tegra186 and later | expand

Commit Message

Thierry Reding Nov. 23, 2018, 12:31 p.m. UTC 
From: Thierry Reding <treding@nvidia.com>

Tegra194 has a version of VIC that is very similar to that on Tegra186.
Add the device tree node for it that is enabled by default.

Signed-off-by: Thierry Reding <treding@nvidia.com>
---
 arch/arm64/boot/dts/nvidia/tegra194.dtsi | 12 ++++++++++++
 1 file changed, 12 insertions(+)
diff mbox series

Patch

diff --git a/arch/arm64/boot/dts/nvidia/tegra194.dtsi b/arch/arm64/boot/dts/nvidia/tegra194.dtsi
index ce7481cb9e5b..19cfddaea697 100644
--- a/arch/arm64/boot/dts/nvidia/tegra194.dtsi
+++ b/arch/arm64/boot/dts/nvidia/tegra194.dtsi
@@ -137,6 +137,18 @@ 
 				};
 			};
 
+			vic@15340000 {
+				compatible = "nvidia,tegra194-vic";
+				reg = <0x15340000 0x00040000>;
+				interrupts = <GIC_SPI 206 IRQ_TYPE_LEVEL_HIGH>;
+				clocks = <&bpmp TEGRA194_CLK_VIC>;
+				clock-names = "vic";
+				resets = <&bpmp TEGRA194_RESET_VIC>;
+				reset-names = "vic";
+
+				power-domains = <&bpmp TEGRA194_POWER_DOMAIN_VIC>;
+			};
+
 			dpaux0: dpaux@155c0000 {
 				compatible = "nvidia,tegra194-dpaux";
 				reg = <0x155c0000 0x10000>;