diff mbox series

[3/3] ARM: tegra: tegra20: Fix mixed tabs-spaces indentation

Message ID 20180718194824.3704-3-krzk@kernel.org
State Deferred
Headers show
Series [1/3] ARM: tegra: apalis-tk1: Fix SPDX license identifier format | expand

Commit Message

Krzysztof Kozlowski July 18, 2018, 7:48 p.m. UTC 
Fix indentation and alignment when spaces were used instead of tabs.
This fixes checkpatch errors like:

    ERROR: code indent should use tabs where possible
    #306: FILE: arch/arm/boot/dts/tegra20-paz00.dts:306:
    +^I^I         <&tegra_car TEGRA20_CLK_PLL_P_OUT3>;$

Signed-off-by: Krzysztof Kozlowski <krzk@kernel.org>
---
 arch/arm/boot/dts/tegra20-colibri.dtsi | 2 +-
 arch/arm/boot/dts/tegra20-paz00.dts    | 6 +++---
 2 files changed, 4 insertions(+), 4 deletions(-)
diff mbox series

Patch

diff --git a/arch/arm/boot/dts/tegra20-colibri.dtsi b/arch/arm/boot/dts/tegra20-colibri.dtsi
index e7b9ab09908a..fa1af2dc276c 100644
--- a/arch/arm/boot/dts/tegra20-colibri.dtsi
+++ b/arch/arm/boot/dts/tegra20-colibri.dtsi
@@ -541,7 +541,7 @@ 
 
 	sound {
 		compatible = "nvidia,tegra-audio-wm9712-colibri_t20",
-			         "nvidia,tegra-audio-wm9712";
+			     "nvidia,tegra-audio-wm9712";
 		nvidia,model = "Colibri T20 AC97 Audio";
 
 		nvidia,audio-routing =
diff --git a/arch/arm/boot/dts/tegra20-paz00.dts b/arch/arm/boot/dts/tegra20-paz00.dts
index ef245291924f..7d8aef6ebd3a 100644
--- a/arch/arm/boot/dts/tegra20-paz00.dts
+++ b/arch/arm/boot/dts/tegra20-paz00.dts
@@ -303,7 +303,7 @@ 
 		request-gpios = <&gpio TEGRA_GPIO(V, 2) GPIO_ACTIVE_HIGH>;
 		slave-addr = <138>;
 		clocks = <&tegra_car TEGRA20_CLK_I2C3>,
-		         <&tegra_car TEGRA20_CLK_PLL_P_OUT3>;
+			 <&tegra_car TEGRA20_CLK_PLL_P_OUT3>;
 		clock-names = "div-clk", "fast-clk";
 		resets = <&tegra_car 67>;
 		reset-names = "i2c";
@@ -599,8 +599,8 @@ 
 			GPIO_ACTIVE_HIGH>;
 
 		clocks = <&tegra_car TEGRA20_CLK_PLL_A>,
-		         <&tegra_car TEGRA20_CLK_PLL_A_OUT0>,
-		         <&tegra_car TEGRA20_CLK_CDEV1>;
+			 <&tegra_car TEGRA20_CLK_PLL_A_OUT0>,
+			 <&tegra_car TEGRA20_CLK_CDEV1>;
 		clock-names = "pll_a", "pll_a_out0", "mclk";
 	};
 };