From patchwork Sun Jun 24 19:22:29 2018 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Stefan Agner X-Patchwork-Id: 933962 Return-Path: X-Original-To: incoming@patchwork.ozlabs.org Delivered-To: patchwork-incoming@bilbo.ozlabs.org Authentication-Results: ozlabs.org; spf=none (mailfrom) smtp.mailfrom=vger.kernel.org (client-ip=209.132.180.67; helo=vger.kernel.org; envelope-from=linux-tegra-owner@vger.kernel.org; receiver=) Authentication-Results: ozlabs.org; dmarc=none (p=none dis=none) header.from=agner.ch Authentication-Results: ozlabs.org; dkim=fail reason="signature verification failed" (1024-bit key; secure) header.d=agner.ch header.i=@agner.ch header.b="Zu+BQa4v"; dkim-atps=neutral Received: from vger.kernel.org (vger.kernel.org [209.132.180.67]) by ozlabs.org (Postfix) with ESMTP id 41DMft6xh7z9s31 for ; Mon, 25 Jun 2018 05:23:50 +1000 (AEST) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1751764AbeFXTXs (ORCPT ); Sun, 24 Jun 2018 15:23:48 -0400 Received: from mail.kmu-office.ch ([178.209.48.109]:36240 "EHLO mail.kmu-office.ch" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1751730AbeFXTWg (ORCPT ); Sun, 24 Jun 2018 15:22:36 -0400 Received: from trochilidae.lan (unknown [IPv6:2a02:169:34d6:10::3]) by mail.kmu-office.ch (Postfix) with ESMTPSA id DF0975C1C1E; Sun, 24 Jun 2018 21:22:33 +0200 (CEST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=agner.ch; s=dkim; t=1529868154; h=from:from:reply-to:subject:subject:date:date:message-id:message-id: to:to:cc:cc:mime-version:content-type:content-transfer-encoding: in-reply-to:in-reply-to:references:references; bh=oofkGP10r8IjuLpXcj0c4x/aJYaNe8KtYGXmfTFU5sU=; b=Zu+BQa4vcG7rt19ouXtGCkmuGRLoJNWbV+/8ItQ91cx5okJAab9TFLUE7Go8VtfqCQzSN3 U+Ux/oslTxCMQXmQJ22Hp78R769RZzKZ1j07SZUu4yOFwi+hAKdwd9yivztaKO5XVO/33V cLnwQn7o//2LAvWrt9QLsiFL7CLkKfI= From: Stefan Agner To: boris.brezillon@bootlin.com, dwmw2@infradead.org, computersforpeace@gmail.com, marek.vasut@gmail.com, robh+dt@kernel.org, mark.rutland@arm.com, thierry.reding@gmail.com Cc: dev@lynxeye.de, miquel.raynal@bootlin.com, richard@nod.at, marcel@ziswiler.com, krzk@kernel.org, digetx@gmail.com, benjamin.lindqvist@endian.se, jonathanh@nvidia.com, pdeschrijver@nvidia.com, pgaikwad@nvidia.com, mirza.krak@gmail.com, gaireg@gaireg.de, linux-mtd@lists.infradead.org, linux-tegra@vger.kernel.org, devicetree@vger.kernel.org, linux-kernel@vger.kernel.org, Stefan Agner Subject: [PATCH v7 5/6] ARM: dts: tegra: add Tegra20 NAND flash controller node Date: Sun, 24 Jun 2018 21:22:29 +0200 Message-Id: <20180624192230.4674-6-stefan@agner.ch> X-Mailer: git-send-email 2.17.1 In-Reply-To: <20180624192230.4674-1-stefan@agner.ch> References: <20180624192230.4674-1-stefan@agner.ch> X-Spamd-Result: default: False [-2.10 / 15.00]; TO_MATCH_ENVRCPT_ALL(0.00)[]; RCPT_COUNT_TWELVE(0.00)[24]; BAYES_HAM(-3.00)[100.00%]; TAGGED_RCPT(0.00)[dt]; MIME_GOOD(-0.10)[text/plain]; FROM_HAS_DN(0.00)[]; FROM_EQ_ENVFROM(0.00)[]; DKIM_SIGNED(0.00)[]; TO_DN_SOME(0.00)[]; RCVD_COUNT_ZERO(0.00)[0]; MID_CONTAINS_FROM(1.00)[]; ASN(0.00)[asn:13030, ipnet:2a02:169::/32, country:CH]; RCVD_TLS_ALL(0.00)[]; ARC_NA(0.00)[] Sender: linux-tegra-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: linux-tegra@vger.kernel.org From: Lucas Stach Add basic controller device tree node to be extended by individual boards. Use the assigned-clocks mechanism to set NDFLASH clock to a sensible default rate of 150MHz. Signed-off-by: Lucas Stach Signed-off-by: Stefan Agner --- arch/arm/boot/dts/tegra20.dtsi | 15 +++++++++++++++ 1 file changed, 15 insertions(+) diff --git a/arch/arm/boot/dts/tegra20.dtsi b/arch/arm/boot/dts/tegra20.dtsi index 983dd5c147945..a75fe7fec7912 100644 --- a/arch/arm/boot/dts/tegra20.dtsi +++ b/arch/arm/boot/dts/tegra20.dtsi @@ -425,6 +425,21 @@ status = "disabled"; }; + nand-controller@70008000 { + compatible = "nvidia,tegra20-nand"; + reg = <0x70008000 0x100>; + #address-cells = <1>; + #size-cells = <0>; + interrupts = ; + clocks = <&tegra_car TEGRA20_CLK_NDFLASH>; + clock-names = "nand"; + resets = <&tegra_car 13>; + reset-names = "nand"; + assigned-clocks = <&tegra_car TEGRA20_CLK_NDFLASH>; + assigned-clock-rates = <150000000>; + status = "disabled"; + }; + pwm: pwm@7000a000 { compatible = "nvidia,tegra20-pwm"; reg = <0x7000a000 0x100>;