From patchwork Thu Jun 23 10:52:31 2016 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Thierry Reding X-Patchwork-Id: 639585 Return-Path: X-Original-To: incoming@patchwork.ozlabs.org Delivered-To: patchwork-incoming@bilbo.ozlabs.org Received: from vger.kernel.org (vger.kernel.org [209.132.180.67]) by ozlabs.org (Postfix) with ESMTP id 3rZywT1080z9syq for ; Thu, 23 Jun 2016 20:52:41 +1000 (AEST) Authentication-Results: ozlabs.org; dkim=fail reason="signature verification failed" (2048-bit key; unprotected) header.d=gmail.com header.i=@gmail.com header.b=jeyTMXwf; dkim-atps=neutral Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1751827AbcFWKwk (ORCPT ); Thu, 23 Jun 2016 06:52:40 -0400 Received: from mail-pf0-f195.google.com ([209.85.192.195]:36670 "EHLO mail-pf0-f195.google.com" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1751816AbcFWKwj (ORCPT ); Thu, 23 Jun 2016 06:52:39 -0400 Received: by mail-pf0-f195.google.com with SMTP id i123so6517657pfg.3; Thu, 23 Jun 2016 03:52:39 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=gmail.com; s=20120113; h=from:to:cc:subject:date:message-id:in-reply-to:references; bh=ALFBAYI3m4yj3sUGFTF6+asf/lJkrXVnmO7GT+WZwOw=; b=jeyTMXwfRsWKCHSxTAGKOK4jaQb/7+z0VaovTUiaTeNzCGAm1GyqMZj+kjpYfzADBp dyISt6PHjjpUpgAuSdEyqBeJTkvlu0dzs36FM4SIDeUb5bw3ArKk/hUPhwn8SKJmbnk8 vohu1wq7OboCxSil22HkZhxaIErb8my5u7PEr8WK1wqwKvJ5Tau5jHzFoLj4ZMOl4kue sw6Ar6FKzw0/xuu3ELIT8N9wjI03xaciGuNx5CW+VdYi1ueSE2AAzWQ3qfC3yamfin2T JmHn4UI1osSoJfCFUCIjYH8cbQe1RV3Z0aoAoZjMZFRDiZQ50dALgDCS0Qq3a161E9xi 7CRg== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20130820; h=x-gm-message-state:from:to:cc:subject:date:message-id:in-reply-to :references; bh=ALFBAYI3m4yj3sUGFTF6+asf/lJkrXVnmO7GT+WZwOw=; b=Alqil1zOOi59jhhdZufbmI5ruGEviACeSm2OrrH2LxhUrayj/p4zl+f3zrBJewVlOJ TCXkubUgv1OBH77qzoBWOWBhoGSLrtay3OiykFvGbH8nBJINkjbY3xiXOs9Rv2HyUHh/ lOBzo8S/DW8IXvIOFxlrHqFIoyVwkngcAJJsFsw3Scd/nuAlSWXgpexGRIG0jkb+Qtik 4MPHYM5sN5a8W2qJbGAx2il9MgkrkcZH/dXA/k5VAbNu21o7IKxEUkJfzvXU7ZcId4EG CzNpGaxoyOqGD3FxaAke8DRMVfEe2iuPxhZ54tIPGqQYQBeC7GXtcidgd55jp0bxm+wY fhNw== X-Gm-Message-State: ALyK8tJuFqPGhTzML/vJfwXwKDhezeyFc467+EuATGHXnd68FZdpY3rsKwyoEoZo96r3NA== X-Received: by 10.98.3.3 with SMTP id 3mr29603721pfd.8.1466679159089; Thu, 23 Jun 2016 03:52:39 -0700 (PDT) Received: from localhost (port-20003.pppoe.wtnet.de. [46.59.139.199]) by smtp.gmail.com with ESMTPSA id 81sm6350250pfo.74.2016.06.23.03.52.37 (version=TLS1_2 cipher=ECDHE-RSA-AES128-GCM-SHA256 bits=128/128); Thu, 23 Jun 2016 03:52:38 -0700 (PDT) From: Thierry Reding To: Thierry Reding Cc: Peter De Schrijver , Rhyland Klein , Jon Hunter , linux-tegra@vger.kernel.org, linux-clk@vger.kernel.org Subject: [PATCH 2/2] clk: tegra: Micro-optimize Tegra210 clock setup Date: Thu, 23 Jun 2016 12:52:31 +0200 Message-Id: <20160623105231.24383-2-thierry.reding@gmail.com> X-Mailer: git-send-email 2.8.3 In-Reply-To: <20160623105231.24383-1-thierry.reding@gmail.com> References: <20160623105231.24383-1-thierry.reding@gmail.com> Sender: linux-tegra-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: linux-tegra@vger.kernel.org From: Thierry Reding sor_safe being the parent of the dpaux and dpaux1 clocks, it's not only natural, but also slightly more efficient, to initialize it before its children. This avoids orphaning the dpaux and dpaux1 clocks only to get them reparented when the sor_safe clock is registered. Signed-off-by: Thierry Reding Acked-by: Jon Hunter Tested-by: Jon Hunter Acked-by: Rhyland Klein --- drivers/clk/tegra/clk-tegra210.c | 8 ++++---- 1 file changed, 4 insertions(+), 4 deletions(-) diff --git a/drivers/clk/tegra/clk-tegra210.c b/drivers/clk/tegra/clk-tegra210.c index fe295b4102ca..b4df5c46642f 100644 --- a/drivers/clk/tegra/clk-tegra210.c +++ b/drivers/clk/tegra/clk-tegra210.c @@ -2466,6 +2466,10 @@ static __init void tegra210_periph_clk_init(void __iomem *clk_base, 1, 2); clks[TEGRA210_CLK_XUSB_SS_DIV2] = clk; + clk = tegra_clk_register_periph_fixed("sor_safe", "pll_p", 0, clk_base, + 1, 17, 222); + clks[TEGRA210_CLK_SOR_SAFE] = clk; + clk = tegra_clk_register_periph_fixed("dpaux", "sor_safe", 0, clk_base, 1, 17, 181); clks[TEGRA210_CLK_DPAUX] = clk; @@ -2474,10 +2478,6 @@ static __init void tegra210_periph_clk_init(void __iomem *clk_base, 1, 17, 207); clks[TEGRA210_CLK_DPAUX1] = clk; - clk = tegra_clk_register_periph_fixed("sor_safe", "pll_p", 0, clk_base, - 1, 17, 222); - clks[TEGRA210_CLK_SOR_SAFE] = clk; - /* pll_d_dsi_out */ clk = clk_register_gate(NULL, "pll_d_dsi_out", "pll_d_out0", 0, clk_base + PLLD_MISC0, 21, 0, &pll_d_lock);