From patchwork Thu Dec 19 12:49:22 2013 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Paul Walmsley X-Patchwork-Id: 303532 Return-Path: X-Original-To: incoming@patchwork.ozlabs.org Delivered-To: patchwork-incoming@bilbo.ozlabs.org Received: from vger.kernel.org (vger.kernel.org [209.132.180.67]) by ozlabs.org (Postfix) with ESMTP id 496512C0089 for ; Thu, 19 Dec 2013 23:49:29 +1100 (EST) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1754624Ab3LSMt2 (ORCPT ); Thu, 19 Dec 2013 07:49:28 -0500 Received: from hqemgate15.nvidia.com ([216.228.121.64]:15878 "EHLO hqemgate15.nvidia.com" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1753525Ab3LSMt0 (ORCPT ); Thu, 19 Dec 2013 07:49:26 -0500 Received: from hqnvupgp07.nvidia.com (Not Verified[216.228.121.13]) by hqemgate15.nvidia.com id ; Thu, 19 Dec 2013 04:49:25 -0800 Received: from hqemhub03.nvidia.com ([172.20.12.94]) by hqnvupgp07.nvidia.com (PGP Universal service); Thu, 19 Dec 2013 04:51:29 -0800 X-PGP-Universal: processed; by hqnvupgp07.nvidia.com on Thu, 19 Dec 2013 04:51:29 -0800 Received: from hqnvemgw01.nvidia.com (172.20.150.20) by HQEMHUB03.nvidia.com (172.20.150.15) with Microsoft SMTP Server id 8.3.327.1; Thu, 19 Dec 2013 04:49:25 -0800 Received: from thelma.nvidia.com (Not Verified[172.16.212.77]) by hqnvemgw01.nvidia.com with MailMarshal (v7,1,2,5326) id ; Thu, 19 Dec 2013 04:49:25 -0800 Received: from [127.0.1.1] (tamien.nvidia.com [172.17.186.57]) by thelma.nvidia.com (8.13.8+Sun/8.8.8) with ESMTP id rBJCnMDw016038; Thu, 19 Dec 2013 04:49:23 -0800 (PST) Subject: [PATCH 4/6] ARM: DTS: tegra: add the DFLL IP block to the T114 SoC file From: Paul Walmsley To: , CC: Mark Rutland , , Pawel Moll , Ian Campbell , Rob Herring , Kumar Gala , Matthew Longnecker Date: Thu, 19 Dec 2013 04:49:22 -0800 Message-ID: <20131219123719.3226.44864.stgit@tamien> In-Reply-To: <20131219122857.3226.42830.stgit@tamien> References: <20131219122857.3226.42830.stgit@tamien> User-Agent: StGit/0.17.1-1-g74fd MIME-Version: 1.0 Sender: linux-tegra-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: linux-tegra@vger.kernel.org Add basic DT bindings for the DFLL IP block for the NVIDIA Tegra114 SoC. Signed-off-by: Paul Walmsley Cc: Matthew Longnecker Cc: Rob Herring Cc: Pawel Moll Cc: Mark Rutland Cc: Ian Campbell Cc: Kumar Gala --- .../bindings/clock/nvidia,tegra114-dfll.txt | 43 ++++++++++++++++++++ arch/arm/boot/dts/tegra114.dtsi | 10 +++++ 2 files changed, 53 insertions(+) create mode 100644 Documentation/devicetree/bindings/clock/nvidia,tegra114-dfll.txt -- To unsubscribe from this list: send the line "unsubscribe linux-tegra" in the body of a message to majordomo@vger.kernel.org More majordomo info at http://vger.kernel.org/majordomo-info.html diff --git a/Documentation/devicetree/bindings/clock/nvidia,tegra114-dfll.txt b/Documentation/devicetree/bindings/clock/nvidia,tegra114-dfll.txt new file mode 100644 index 000000000000..b868bf97bc3d --- /dev/null +++ b/Documentation/devicetree/bindings/clock/nvidia,tegra114-dfll.txt @@ -0,0 +1,43 @@ +NVIDIA Tegra114 DFLL FCPU clocksource data in the SoC DTS file: + +Required properties: + +- compatible : "nvidia,tegra114-dfll-fcpu" + +- reg : Must contain the starting physical address and length for the + DFLL's MMIO register space, including the DFLL-to-I2C + controller interface and the DFLL's I2C controller. + +- clocks : Must contain an array of two-cell arrays, one per clock. + DFLL source clocks. At minimum this should include the + reference clock source and the IP block's main clock + source. Also it should contain the DFLL's I2C controller + clock source. The format is <&clock-provider-phandle + clock-id>. + +- clock-names : Must contain an array of strings, one per 'clocks' + two-cell array. The position in the array of these + strings must correspond to the position in the 'clocks' + array (see above). The DFLL driver currently requires + the "soc", "ref", and "i2c" clock names to be populated. + + +Optional properties: + +- status : device availability -- managed by the DT integration code, not + the DFLL driver. Should be set to "disabled" in the SoC + DTS file. + + +Example: + +dfll@70110000 { + compatible = "nvidia,tegra114-dfll-fcpu"; + reg = <0x70110000 0x400>; + clocks = <&tegra_car TEGRA114_CLK_DFLL_SOC>, + <&tegra_car TEGRA114_CLK_DFLL_REF>, + <&tegra_car TEGRA114_CLK_I2C5>; + clock-names = "soc", "ref", "i2c"; + status = "disabled"; +}; + diff --git a/arch/arm/boot/dts/tegra114.dtsi b/arch/arm/boot/dts/tegra114.dtsi index ae855ec60bbd..1cd59d79e67c 100644 --- a/arch/arm/boot/dts/tegra114.dtsi +++ b/arch/arm/boot/dts/tegra114.dtsi @@ -480,6 +480,16 @@ }; }; + dfll@70110000 { + compatible = "nvidia,tegra114-dfll-fcpu"; + reg = <0x70110000 0x400>; + clocks = <&tegra_car TEGRA114_CLK_DFLL_SOC>, + <&tegra_car TEGRA114_CLK_DFLL_REF>, + <&tegra_car TEGRA114_CLK_I2C5>; + clock-names = "soc", "ref", "i2c"; + status = "disabled"; + }; + sdhci@78000000 { compatible = "nvidia,tegra114-sdhci", "nvidia,tegra30-sdhci"; reg = <0x78000000 0x200>;