From patchwork Mon Aug 12 11:28:16 2019 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Krishna Yarlagadda X-Patchwork-Id: 1145672 Return-Path: X-Original-To: incoming@patchwork.ozlabs.org Delivered-To: patchwork-incoming@bilbo.ozlabs.org Authentication-Results: ozlabs.org; spf=none (mailfrom) smtp.mailfrom=vger.kernel.org (client-ip=209.132.180.67; helo=vger.kernel.org; envelope-from=linux-tegra-owner@vger.kernel.org; receiver=) Authentication-Results: ozlabs.org; dmarc=pass (p=none dis=none) header.from=nvidia.com Authentication-Results: ozlabs.org; dkim=pass (2048-bit key; unprotected) header.d=nvidia.com header.i=@nvidia.com header.b="TO9wVyVo"; dkim-atps=neutral Received: from vger.kernel.org (vger.kernel.org [209.132.180.67]) by ozlabs.org (Postfix) with ESMTP id 466YXk04J5z9sPV for ; Mon, 12 Aug 2019 21:29:42 +1000 (AEST) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1728536AbfHLL3E (ORCPT ); Mon, 12 Aug 2019 07:29:04 -0400 Received: from hqemgate15.nvidia.com ([216.228.121.64]:18444 "EHLO hqemgate15.nvidia.com" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1728525AbfHLL3D (ORCPT ); Mon, 12 Aug 2019 07:29:03 -0400 Received: from hqpgpgate102.nvidia.com (Not Verified[216.228.121.13]) by hqemgate15.nvidia.com (using TLS: TLSv1.2, DES-CBC3-SHA) id ; Mon, 12 Aug 2019 04:29:14 -0700 Received: from hqmail.nvidia.com ([172.20.161.6]) by hqpgpgate102.nvidia.com (PGP Universal service); Mon, 12 Aug 2019 04:29:03 -0700 X-PGP-Universal: processed; by hqpgpgate102.nvidia.com on Mon, 12 Aug 2019 04:29:03 -0700 Received: from HQMAIL101.nvidia.com (172.20.187.10) by HQMAIL107.nvidia.com (172.20.187.13) with Microsoft SMTP Server (TLS) id 15.0.1473.3; Mon, 12 Aug 2019 11:29:02 +0000 Received: from hqnvemgw02.nvidia.com (172.16.227.111) by HQMAIL101.nvidia.com (172.20.187.10) with Microsoft SMTP Server (TLS) id 15.0.1473.3 via Frontend Transport; Mon, 12 Aug 2019 11:29:02 +0000 Received: from kyarlagadda-linux.nvidia.com (Not Verified[10.19.64.169]) by hqnvemgw02.nvidia.com with Trustwave SEG (v7, 5, 8, 10121) id ; Mon, 12 Aug 2019 04:29:02 -0700 From: Krishna Yarlagadda To: , , , , , , CC: , , , , Krishna Yarlagadda Subject: [PATCH 07/14] serial: tegra: add compatible for new chips Date: Mon, 12 Aug 2019 16:58:16 +0530 Message-ID: <1565609303-27000-8-git-send-email-kyarlagadda@nvidia.com> X-Mailer: git-send-email 2.7.4 In-Reply-To: <1565609303-27000-1-git-send-email-kyarlagadda@nvidia.com> References: <1565609303-27000-1-git-send-email-kyarlagadda@nvidia.com> X-NVConfidentiality: public MIME-Version: 1.0 DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=nvidia.com; s=n1; t=1565609354; bh=xUV7cCxrNBKpWRz8LPBZJwzzZhog/ITvNlddt3ERxp8=; h=X-PGP-Universal:From:To:CC:Subject:Date:Message-ID:X-Mailer: In-Reply-To:References:X-NVConfidentiality:MIME-Version: Content-Type; b=TO9wVyVo9F0QArP5Fut2YL0fK80qmtM4SPMSt4tayGOf/dgXj6Ughh8DE6Xal2Iw6 6Bnbw+Z7Q+q6FUvKQk3C2E3ypqpvMiEQS3Kf+MFNUVOFvv8l9y1QRytg+n4AHEg9Yj QAnhXTNGqPb31v2N3HQDWUwlImLV0lBf/OmVmshYuxOq/vLSDjisTThVDdKp5wO+sL bf8e4JJ+HdaYYEXEcC3lArr95o4vuKG/waa7vDAxeevwYgpqn/5wtyPP0bIHtsjHRu N90A9JJrZNRQCSSyMMIehrK156ArTq8pUkG5t8QnYhENYx+5CJjKuW0umrL/398iUC guqJf2dW2nXqA== Sender: linux-tegra-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: linux-tegra@vger.kernel.org Add new compatible string for Tegra186. It differs from earlier chips as it has fifo mode enable check and 8 byte dma buffer. Add new compatible string for Tegra194. Tegra194 has different error tolerance levels for baud rate compared to older chips. Signed-off-by: Krishna Yarlagadda --- Documentation/devicetree/bindings/serial/nvidia,tegra20-hsuart.txt | 3 ++- 1 file changed, 2 insertions(+), 1 deletion(-) diff --git a/Documentation/devicetree/bindings/serial/nvidia,tegra20-hsuart.txt b/Documentation/devicetree/bindings/serial/nvidia,tegra20-hsuart.txt index d7edf73..187ec78 100644 --- a/Documentation/devicetree/bindings/serial/nvidia,tegra20-hsuart.txt +++ b/Documentation/devicetree/bindings/serial/nvidia,tegra20-hsuart.txt @@ -1,7 +1,8 @@ NVIDIA Tegra20/Tegra30 high speed (DMA based) UART controller driver. Required properties: -- compatible : should be "nvidia,tegra30-hsuart", "nvidia,tegra20-hsuart". +- compatible : should be "nvidia,tegra30-hsuart", "nvidia,tegra20-hsuart", + nvidia,tegra186-hsuart, nvidia,tegra194-hsuart. - reg: Should contain UART controller registers location and length. - interrupts: Should contain UART controller interrupts. - clocks: Must contain one entry, for the module clock.