From patchwork Tue May 28 23:08:55 2019 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Sowjanya Komatineni X-Patchwork-Id: 1106600 Return-Path: X-Original-To: incoming@patchwork.ozlabs.org Delivered-To: patchwork-incoming@bilbo.ozlabs.org Authentication-Results: ozlabs.org; spf=none (mailfrom) smtp.mailfrom=vger.kernel.org (client-ip=209.132.180.67; helo=vger.kernel.org; envelope-from=linux-tegra-owner@vger.kernel.org; receiver=) Authentication-Results: ozlabs.org; dmarc=pass (p=none dis=none) header.from=nvidia.com Authentication-Results: ozlabs.org; dkim=pass (2048-bit key; unprotected) header.d=nvidia.com header.i=@nvidia.com header.b="LovV5aJ0"; dkim-atps=neutral Received: from vger.kernel.org (vger.kernel.org [209.132.180.67]) by ozlabs.org (Postfix) with ESMTP id 45D8g31XJMz9s4V for ; Wed, 29 May 2019 09:09:19 +1000 (AEST) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1727605AbfE1XJN (ORCPT ); Tue, 28 May 2019 19:09:13 -0400 Received: from hqemgate15.nvidia.com ([216.228.121.64]:11196 "EHLO hqemgate15.nvidia.com" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1727624AbfE1XJE (ORCPT ); Tue, 28 May 2019 19:09:04 -0400 Received: from hqpgpgate101.nvidia.com (Not Verified[216.228.121.13]) by hqemgate15.nvidia.com (using TLS: TLSv1.2, DES-CBC3-SHA) id ; Tue, 28 May 2019 16:08:53 -0700 Received: from hqmail.nvidia.com ([172.20.161.6]) by hqpgpgate101.nvidia.com (PGP Universal service); Tue, 28 May 2019 16:09:01 -0700 X-PGP-Universal: processed; by hqpgpgate101.nvidia.com on Tue, 28 May 2019 16:09:01 -0700 Received: from HQMAIL107.nvidia.com (172.20.187.13) by HQMAIL107.nvidia.com (172.20.187.13) with Microsoft SMTP Server (TLS) id 15.0.1473.3; Tue, 28 May 2019 23:09:01 +0000 Received: from hqnvemgw01.nvidia.com (172.20.150.20) by HQMAIL107.nvidia.com (172.20.187.13) with Microsoft SMTP Server (TLS) id 15.0.1473.3 via Frontend Transport; Tue, 28 May 2019 23:09:01 +0000 Received: from skomatineni-linux.nvidia.com (Not Verified[10.110.103.86]) by hqnvemgw01.nvidia.com with Trustwave SEG (v7, 5, 8, 10121) id ; Tue, 28 May 2019 16:09:00 -0700 From: Sowjanya Komatineni To: , , , , , , , CC: , , , , , , , , , , , , , , Subject: [PATCH V2 11/12] arm64: tegra: enable wake from deep sleep on RTC alarm. Date: Tue, 28 May 2019 16:08:55 -0700 Message-ID: <1559084936-4610-12-git-send-email-skomatineni@nvidia.com> X-Mailer: git-send-email 2.7.4 In-Reply-To: <1559084936-4610-1-git-send-email-skomatineni@nvidia.com> References: <1559084936-4610-1-git-send-email-skomatineni@nvidia.com> X-NVConfidentiality: public MIME-Version: 1.0 DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=nvidia.com; s=n1; t=1559084933; bh=0l4gC+Qj0JmgYVzpD51BKCVjV4o0qtIe+OiFzC2IyHA=; h=X-PGP-Universal:From:To:CC:Subject:Date:Message-ID:X-Mailer: In-Reply-To:References:X-NVConfidentiality:MIME-Version: Content-Type; b=LovV5aJ0tEX82byBH3tCz6/VwLbrK1FSYX/Z3Ng4spRzao8ATjbMWMNVGsFc+xLNv 88j5TkQTl77TkvLcNJrlf+fq8hsKZAISyoJIUgB4Tc7cYIhZdQRjvQY5Y9MZMHlCyu c5x4iQ+eeVJXqZtGsNNjjRNvFOsrewPLiPiCrmya+6Wy7ek/mQbT1YVNMBPY1EgadK RQuRTqJpw5nmgTJws0TmztcOAoF6TmiDV7+BtVLDc2dVr4cS0raKs3jwr+IxNG3/Nl Mw24jBRxE8w/pujebCbHSKlyAa6gkQzPCAaSVz/3GgFH3EqpBPwXzlFV6dThrqG3VO 12pn60KwfVRtg== Sender: linux-tegra-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: linux-tegra@vger.kernel.org This patch updates device tree for RTC and PMC to allow system wake from deep sleep on RTC alarm. Signed-off-by: Sowjanya Komatineni --- arch/arm64/boot/dts/nvidia/tegra210.dtsi | 5 ++++- 1 file changed, 4 insertions(+), 1 deletion(-) diff --git a/arch/arm64/boot/dts/nvidia/tegra210.dtsi b/arch/arm64/boot/dts/nvidia/tegra210.dtsi index a550c0a4d572..cf5c215efb04 100644 --- a/arch/arm64/boot/dts/nvidia/tegra210.dtsi +++ b/arch/arm64/boot/dts/nvidia/tegra210.dtsi @@ -763,7 +763,8 @@ rtc@7000e000 { compatible = "nvidia,tegra210-rtc", "nvidia,tegra20-rtc"; reg = <0x0 0x7000e000 0x0 0x100>; - interrupts = ; + interrupts = <16 IRQ_TYPE_LEVEL_HIGH>; + interrupt-parent = <&pmc>; clocks = <&tegra_car TEGRA210_CLK_RTC>; clock-names = "rtc"; }; @@ -773,6 +774,8 @@ reg = <0x0 0x7000e400 0x0 0x400>; clocks = <&tegra_car TEGRA210_CLK_PCLK>, <&clk32k_in>; clock-names = "pclk", "clk32k_in"; + #interrupt-cells = <2>; + interrupt-controller; powergates { pd_audio: aud {