[V1,09/26] spi: tegra114: dump SPI registers during timeout

Message ID	1553666207-11414-9-git-send-email-skomatineni@nvidia.com
State	Changes Requested
Headers	show Return-Path: <linux-tegra-owner@vger.kernel.org> TLS: TLSv1.2, DES-CBC3-SHA) id <B5c9b10bb0000>; Tue, 26 Mar 2019 22:57:15 -0700 From: Sowjanya Komatineni <skomatineni@nvidia.com> To: <thierry.reding@gmail.com>, <jonathanh@nvidia.com>, <talho@nvidia.com>, <skomatineni@nvidia.com>, <broonie@kernel.org>, <robh+dt@kernel.org>, <mark.rutland@arm.com>, <kyarlagadda@nvidia.com> CC: <ldewangan@nvidia.com>, <linux-tegra@vger.kernel.org>, <linux-kernel@vger.kernel.org>, <linux-spi@vger.kernel.org>, <devicetree@vger.kernel.org> Subject: [PATCH V1 09/26] spi: tegra114: dump SPI registers during timeout Date: Tue, 26 Mar 2019 22:56:30 -0700 Message-ID: <1553666207-11414-9-git-send-email-skomatineni@nvidia.com> In-Reply-To: <1553666207-11414-1-git-send-email-skomatineni@nvidia.com> References: <1553666207-11414-1-git-send-email-skomatineni@nvidia.com> MIME-Version: 1.0 Content-Type: text/plain Sender: linux-tegra-owner@vger.kernel.org Precedence: bulk
Series	[V1,01/26] spi: tegra114: fix PIO transfer \| expand [V1,01/26] spi: tegra114: fix PIO transfer [V1,02/26] spi: tegra114: clear packed bit for unpacked mode [V1,03/26] spi: tegra114: fix for unpacked mode transfers [V1,04/26] spi: tegra114: use packed mode for 32 bits per word [V1,05/26] spi: tegra114: use unpacked mode for below 4 byte transfers [V1,06/26] spi: tegra114: terminate dma and reset on transfer timeout [V1,07/26] spi: tegra114: flush fifos [V1,08/26] spi: tegra114: configure dma burst size to fifo trig level [V1,09/26] spi: tegra114: dump SPI registers during timeout [V1,10/26] spi: tegra114: avoid reset call in atomic context [V1,11/26] spi: tegra114: reset controller on probe [V1,12/26] spi: tegra114: add SPI_LSB_FIRST support [V1,13/26] spi: tegra114: add dual mode support [V1,14/26] spi: tegra114: add 3 wire transfer mode support [V1,15/26] spi: tegra114: set supported bits_per_word [V1,16/26] spi: tegra114: set bus number based on id [V1,17/26] spi: tegra114: add support for interrupt mask [V1,18/26] spi: tegra114: add support for hw based cs [V1,19/26] DT bindings: spi: add spi client device properties [V1,20/26] spi: tegra114: add support for tuning HW CS timing [V1,21/26] DT bindings: spi: add tx/rx clock delay SPI client properties [V1,22/26] spi: tegra114: add support for tuning clock delay [V1,23/26] spi: tegra114: add support for gpio based cs [V1,24/26] spi: tegra114: de-assert CS before SPI mode is reset to its default [V1,25/26] spi: expand mode and mode_bits support [V1,26/26] spi: tegra114: add support for LSBYTE_FIRST

Message ID

1553666207-11414-9-git-send-email-skomatineni@nvidia.com

State

Changes Requested

Headers

From: Sowjanya Komatineni <skomatineni@nvidia.com>
To: <thierry.reding@gmail.com>, <jonathanh@nvidia.com>,
	<talho@nvidia.com>, <skomatineni@nvidia.com>, <broonie@kernel.org>,
	<robh+dt@kernel.org>, <mark.rutland@arm.com>, <kyarlagadda@nvidia.com>
CC: <ldewangan@nvidia.com>, <linux-tegra@vger.kernel.org>,
	<linux-kernel@vger.kernel.org>, <linux-spi@vger.kernel.org>,
	<devicetree@vger.kernel.org>
Subject: [PATCH V1 09/26] spi: tegra114: dump SPI registers during timeout
Date: Tue, 26 Mar 2019 22:56:30 -0700
Message-ID: <1553666207-11414-9-git-send-email-skomatineni@nvidia.com>
In-Reply-To: <1553666207-11414-1-git-send-email-skomatineni@nvidia.com>
References: <1553666207-11414-1-git-send-email-skomatineni@nvidia.com>
MIME-Version: 1.0
Content-Type: text/plain
Sender: linux-tegra-owner@vger.kernel.org
Precedence: bulk

Series

[V1,01/26] spi: tegra114: fix PIO transfer | expand

This patch dumps SPI registers on DMA or transfer timeout for debug purpose. Signed-off-by: Sowjanya Komatineni <skomatineni@nvidia.com> --- drivers/spi/spi-tegra114.c | 18 ++++++++++++++++++ 1 file changed, 18 insertions(+)

Comments

Mark Brown April 1, 2019, 7:39 a.m. UTC | #1

On Tue, Mar 26, 2019 at 10:56:30PM -0700, Sowjanya Komatineni wrote:
> This patch dumps SPI registers on DMA or transfer timeout for debug
> purpose.

This is another non-bugfix patch which should be after the bugfixes.

diff --git a/drivers/spi/spi-tegra114.c b/drivers/spi/spi-tegra114.c
index b7e71676a506..268a790a663e 100644
--- a/drivers/spi/spi-tegra114.c
+++ b/drivers/spi/spi-tegra114.c
@@ -858,6 +858,20 @@  static void tegra_spi_transfer_delay(int delay)
 	udelay(delay % 1000);
 }
 
+static void tegra_spi_dump_regs(struct tegra_spi_data *tspi)
+{
+	dev_dbg(tspi->dev, "============ SPI REGISTER DUMP ============\n");
+	dev_dbg(tspi->dev, "Command1:    0x%08x | Command2:    0x%08x\n",
+		tegra_spi_readl(tspi, SPI_COMMAND1),
+		tegra_spi_readl(tspi, SPI_COMMAND2));
+	dev_dbg(tspi->dev, "DMA_CTL:     0x%08x | DMA_BLK:     0x%08x\n",
+		tegra_spi_readl(tspi, SPI_DMA_CTL),
+		tegra_spi_readl(tspi, SPI_DMA_BLK));
+	dev_dbg(tspi->dev, "TRANS_STAT:  0x%08x | FIFO_STATUS: 0x%08x\n",
+		tegra_spi_readl(tspi, SPI_TRANS_STATUS),
+		tegra_spi_readl(tspi, SPI_FIFO_STATUS));
+}
+
 static int tegra_spi_transfer_one_message(struct spi_master *master,
 			struct spi_message *msg)
 {
@@ -904,6 +918,7 @@  static int tegra_spi_transfer_one_message(struct spi_master *master,
 			    (tspi->cur_direction & DATA_DIR_RX))
 				dmaengine_terminate_all(tspi->rx_dma_chan);
 			ret = -EIO;
+			tegra_spi_dump_regs(tspi);
 			tegra_spi_flush_fifos(tspi);
 			reset_control_assert(tspi->rst);
 			udelay(2);
@@ -913,6 +928,7 @@  static int tegra_spi_transfer_one_message(struct spi_master *master,
 
 		if (tspi->tx_status ||  tspi->rx_status) {
 			dev_err(tspi->dev, "Error in Transfer\n");
+			tegra_spi_dump_regs(tspi);
 			ret = -EIO;
 			goto complete_xfer;
 		}
@@ -958,6 +974,7 @@  static irqreturn_t handle_cpu_based_xfer(struct tegra_spi_data *tspi)
 			tspi->status_reg);
 		dev_err(tspi->dev, "CpuXfer 0x%08x:0x%08x\n",
 			tspi->command1_reg, tspi->dma_control_reg);
+		tegra_spi_dump_regs(tspi);
 		tegra_spi_flush_fifos(tspi);
 		reset_control_assert(tspi->rst);
 		udelay(2);
@@ -1031,6 +1048,7 @@  static irqreturn_t handle_dma_based_xfer(struct tegra_spi_data *tspi)
 			tspi->status_reg);
 		dev_err(tspi->dev, "DmaXfer 0x%08x:0x%08x\n",
 			tspi->command1_reg, tspi->dma_control_reg);
+		tegra_spi_dump_regs(tspi);
 		tegra_spi_flush_fifos(tspi);
 		reset_control_assert(tspi->rst);
 		udelay(2);

[V1,09/26] spi: tegra114: dump SPI registers during timeout

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