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[V1,15/26] spi: tegra114: set supported bits_per_word

Message ID	1553666207-11414-15-git-send-email-skomatineni@nvidia.com
State	Changes Requested
Headers	show Return-Path: <linux-tegra-owner@vger.kernel.org> TLS: TLSv1.2, DES-CBC3-SHA) id <B5c9b10c60000>; Tue, 26 Mar 2019 22:57:26 -0700 From: Sowjanya Komatineni <skomatineni@nvidia.com> To: <thierry.reding@gmail.com>, <jonathanh@nvidia.com>, <talho@nvidia.com>, <skomatineni@nvidia.com>, <broonie@kernel.org>, <robh+dt@kernel.org>, <mark.rutland@arm.com>, <kyarlagadda@nvidia.com> CC: <ldewangan@nvidia.com>, <linux-tegra@vger.kernel.org>, <linux-kernel@vger.kernel.org>, <linux-spi@vger.kernel.org>, <devicetree@vger.kernel.org> Subject: [PATCH V1 15/26] spi: tegra114: set supported bits_per_word Date: Tue, 26 Mar 2019 22:56:36 -0700 Message-ID: <1553666207-11414-15-git-send-email-skomatineni@nvidia.com> In-Reply-To: <1553666207-11414-1-git-send-email-skomatineni@nvidia.com> References: <1553666207-11414-1-git-send-email-skomatineni@nvidia.com> MIME-Version: 1.0 Content-Type: text/plain Sender: linux-tegra-owner@vger.kernel.org Precedence: bulk
Series	[V1,01/26] spi: tegra114: fix PIO transfer \| expand [V1,01/26] spi: tegra114: fix PIO transfer [V1,02/26] spi: tegra114: clear packed bit for unpacked mode [V1,03/26] spi: tegra114: fix for unpacked mode transfers [V1,04/26] spi: tegra114: use packed mode for 32 bits per word [V1,05/26] spi: tegra114: use unpacked mode for below 4 byte transfers [V1,06/26] spi: tegra114: terminate dma and reset on transfer timeout [V1,07/26] spi: tegra114: flush fifos [V1,08/26] spi: tegra114: configure dma burst size to fifo trig level [V1,09/26] spi: tegra114: dump SPI registers during timeout [V1,10/26] spi: tegra114: avoid reset call in atomic context [V1,11/26] spi: tegra114: reset controller on probe [V1,12/26] spi: tegra114: add SPI_LSB_FIRST support [V1,13/26] spi: tegra114: add dual mode support [V1,14/26] spi: tegra114: add 3 wire transfer mode support [V1,15/26] spi: tegra114: set supported bits_per_word [V1,16/26] spi: tegra114: set bus number based on id [V1,17/26] spi: tegra114: add support for interrupt mask [V1,18/26] spi: tegra114: add support for hw based cs [V1,19/26] DT bindings: spi: add spi client device properties [V1,20/26] spi: tegra114: add support for tuning HW CS timing [V1,21/26] DT bindings: spi: add tx/rx clock delay SPI client properties [V1,22/26] spi: tegra114: add support for tuning clock delay [V1,23/26] spi: tegra114: add support for gpio based cs [V1,24/26] spi: tegra114: de-assert CS before SPI mode is reset to its default [V1,25/26] spi: expand mode and mode_bits support [V1,26/26] spi: tegra114: add support for LSBYTE_FIRST

Commit Message

Sowjanya Komatineni March 27, 2019, 5:56 a.m. UTC

Tegra SPI supports 4 through 32 bits per word.

This patch sets bits_per_word_mask accordingly to support transfer
with these bits per word.

Signed-off-by: Sowjanya Komatineni <skomatineni@nvidia.com>
---
 drivers/spi/spi-tegra114.c | 1 +
 1 file changed, 1 insertion(+)

diff mbox series

Patch

diff --git a/drivers/spi/spi-tegra114.c b/drivers/spi/spi-tegra114.c
index 01efb615a196..94acef0f5ea5 100644
--- a/drivers/spi/spi-tegra114.c
+++ b/drivers/spi/spi-tegra114.c
@@ -1154,6 +1154,7 @@  static int tegra_spi_probe(struct platform_device *pdev)
 	/* the spi->mode bits understood by this driver: */
 	master->mode_bits = SPI_CPOL | SPI_CPHA | SPI_CS_HIGH | SPI_LSB_FIRST |
 			    SPI_TX_DUAL | SPI_RX_DUAL | SPI_3WIRE;
+	master->bits_per_word_mask = SPI_BPW_RANGE_MASK(4, 32);
 	master->setup = tegra_spi_setup;
 	master->transfer_one_message = tegra_spi_transfer_one_message;
 	master->num_chipselect = MAX_CHIP_SELECT;