Message ID | 1553666207-11414-1-git-send-email-skomatineni@nvidia.com |
---|---|
State | Changes Requested |
Headers | show
Return-Path: <linux-tegra-owner@vger.kernel.org> X-Original-To: incoming@patchwork.ozlabs.org Delivered-To: patchwork-incoming@bilbo.ozlabs.org Authentication-Results: ozlabs.org; spf=none (mailfrom) smtp.mailfrom=vger.kernel.org (client-ip=209.132.180.67; helo=vger.kernel.org; envelope-from=linux-tegra-owner@vger.kernel.org; receiver=<UNKNOWN>) Authentication-Results: ozlabs.org; dmarc=pass (p=none dis=none) header.from=nvidia.com Authentication-Results: ozlabs.org; dkim=pass (2048-bit key; unprotected) header.d=nvidia.com header.i=@nvidia.com header.b="ZpJwqJdj"; dkim-atps=neutral Received: from vger.kernel.org (vger.kernel.org [209.132.180.67]) by ozlabs.org (Postfix) with ESMTP id 44TclQ2wJBz9sRW for <incoming@patchwork.ozlabs.org>; Wed, 27 Mar 2019 16:59:30 +1100 (AEDT) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1725841AbfC0F5D (ORCPT <rfc822;incoming@patchwork.ozlabs.org>); Wed, 27 Mar 2019 01:57:03 -0400 Received: from hqemgate15.nvidia.com ([216.228.121.64]:6957 "EHLO hqemgate15.nvidia.com" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1725772AbfC0F5C (ORCPT <rfc822;linux-tegra@vger.kernel.org>); Wed, 27 Mar 2019 01:57:02 -0400 Received: from hqpgpgate101.nvidia.com (Not Verified[216.228.121.13]) by hqemgate15.nvidia.com (using TLS: TLSv1.2, DES-CBC3-SHA) id <B5c9b10a90000>; Tue, 26 Mar 2019 22:56:57 -0700 Received: from hqmail.nvidia.com ([172.20.161.6]) by hqpgpgate101.nvidia.com (PGP Universal service); Tue, 26 Mar 2019 22:57:02 -0700 X-PGP-Universal: processed; by hqpgpgate101.nvidia.com on Tue, 26 Mar 2019 22:57:02 -0700 Received: from HQMAIL111.nvidia.com (172.20.187.18) by HQMAIL106.nvidia.com (172.18.146.12) with Microsoft SMTP Server (TLS) id 15.0.1473.3; Wed, 27 Mar 2019 05:57:01 +0000 Received: from HQMAIL106.nvidia.com (172.18.146.12) by HQMAIL111.nvidia.com (172.20.187.18) with Microsoft SMTP Server (TLS) id 15.0.1473.3; Wed, 27 Mar 2019 05:57:01 +0000 Received: from hqnvemgw01.nvidia.com (172.20.150.20) by HQMAIL106.nvidia.com (172.18.146.12) with Microsoft SMTP Server (TLS) id 15.0.1473.3 via Frontend Transport; Wed, 27 Mar 2019 05:57:01 +0000 Received: from skomatineni-linux.nvidia.com (Not Verified[10.2.161.83]) by hqnvemgw01.nvidia.com with Trustwave SEG (v7, 5, 8, 10121) id <B5c9b10ab0001>; Tue, 26 Mar 2019 22:57:00 -0700 From: Sowjanya Komatineni <skomatineni@nvidia.com> To: <thierry.reding@gmail.com>, <jonathanh@nvidia.com>, <talho@nvidia.com>, <skomatineni@nvidia.com>, <broonie@kernel.org>, <robh+dt@kernel.org>, <mark.rutland@arm.com>, <kyarlagadda@nvidia.com> CC: <ldewangan@nvidia.com>, <linux-tegra@vger.kernel.org>, <linux-kernel@vger.kernel.org>, <linux-spi@vger.kernel.org>, <devicetree@vger.kernel.org> Subject: [PATCH V1 01/26] spi: tegra114: fix PIO transfer Date: Tue, 26 Mar 2019 22:56:22 -0700 Message-ID: <1553666207-11414-1-git-send-email-skomatineni@nvidia.com> X-Mailer: git-send-email 2.7.4 X-NVConfidentiality: public MIME-Version: 1.0 Content-Type: text/plain DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=nvidia.com; s=n1; t=1553666217; bh=jnKCDS2+fDqhI4VcNWBwJ5VdZIxqBkvA13qxpCzyHjg=; h=X-PGP-Universal:From:To:CC:Subject:Date:Message-ID:X-Mailer: X-NVConfidentiality:MIME-Version:Content-Type; b=ZpJwqJdjFA+Uhw1ZZzUlNOH9xPq8lNWqN0BCcrgV0ay9r2/zvsC5AN1iauaAGae98 TU6U/8UxcUoKDp/28KufsxY1mXQ/QwjxHPCYv4QYorMwngIMTkq4ByGCMpobfR0xs+ I4vPKTLBg83EjDiqOL9s6ypznbV+dy1HL6itryNldrrOaAp5E/RbSE/xyGKzbT8Ojo M1oMEs1rucqt1co9ty7dkpc1ObJcjrfAX869o5J8SEKqOuR/L+1OG5pBZrfBh92xfm mXh0PM9ObD7UE8PuAxiRywnahDxLv9faOvBdBYZtJyfDBYWWIkIykAl2xadyCDLiRq h93BjKvMBcu4g== Sender: linux-tegra-owner@vger.kernel.org Precedence: bulk List-ID: <linux-tegra.vger.kernel.org> X-Mailing-List: linux-tegra@vger.kernel.org |
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[V1,01/26] spi: tegra114: fix PIO transfer
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diff --git a/drivers/spi/spi-tegra114.c b/drivers/spi/spi-tegra114.c index a76acedd7e2f..5a21bc808bb6 100644 --- a/drivers/spi/spi-tegra114.c +++ b/drivers/spi/spi-tegra114.c @@ -570,8 +570,9 @@ static int tegra_spi_start_cpu_based_transfer( tspi->is_curr_dma_xfer = false; - val |= SPI_DMA_EN; - tegra_spi_writel(tspi, val, SPI_DMA_CTL); + val = tspi->command1_reg; + val |= SPI_PIO; + tegra_spi_writel(tspi, val, SPI_COMMAND1); return 0; }
Fixes: Use PIO bit in SPI_COMMAND1 register for PIO mode. Current driver uses DMA_EN instead of PIO bit. Signed-off-by: Sowjanya Komatineni <skomatineni@nvidia.com> --- drivers/spi/spi-tegra114.c | 5 +++-- 1 file changed, 3 insertions(+), 2 deletions(-)