From patchwork Thu Jan 24 17:03:55 2019 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Timo Alho X-Patchwork-Id: 1030579 Return-Path: X-Original-To: incoming@patchwork.ozlabs.org Delivered-To: patchwork-incoming@bilbo.ozlabs.org Authentication-Results: ozlabs.org; spf=none (mailfrom) smtp.mailfrom=vger.kernel.org (client-ip=209.132.180.67; helo=vger.kernel.org; envelope-from=linux-tegra-owner@vger.kernel.org; receiver=) Authentication-Results: ozlabs.org; dmarc=pass (p=none dis=none) header.from=nvidia.com Authentication-Results: ozlabs.org; dkim=pass (2048-bit key; unprotected) header.d=nvidia.com header.i=@nvidia.com header.b="BRENgec+"; dkim-atps=neutral Received: from vger.kernel.org (vger.kernel.org [209.132.180.67]) by ozlabs.org (Postfix) with ESMTP id 43lpQy55h1z9s9G for ; Fri, 25 Jan 2019 04:04:10 +1100 (AEDT) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1728818AbfAXREK (ORCPT ); Thu, 24 Jan 2019 12:04:10 -0500 Received: from hqemgate14.nvidia.com ([216.228.121.143]:5820 "EHLO hqemgate14.nvidia.com" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1728779AbfAXREK (ORCPT ); Thu, 24 Jan 2019 12:04:10 -0500 Received: from hqpgpgate102.nvidia.com (Not Verified[216.228.121.13]) by hqemgate14.nvidia.com (using TLS: TLSv1.2, DES-CBC3-SHA) id ; Thu, 24 Jan 2019 09:03:51 -0800 Received: from hqmail.nvidia.com ([172.20.161.6]) by hqpgpgate102.nvidia.com (PGP Universal service); Thu, 24 Jan 2019 09:04:09 -0800 X-PGP-Universal: processed; by hqpgpgate102.nvidia.com on Thu, 24 Jan 2019 09:04:09 -0800 Received: from HQMAIL106.nvidia.com (172.18.146.12) by HQMAIL104.nvidia.com (172.18.146.11) with Microsoft SMTP Server (TLS) id 15.0.1395.4; Thu, 24 Jan 2019 17:04:09 +0000 Received: from hqnvemgw02.nvidia.com (172.16.227.111) by HQMAIL106.nvidia.com (172.18.146.12) with Microsoft SMTP Server (TLS) id 15.0.1395.4 via Frontend Transport; Thu, 24 Jan 2019 17:04:08 +0000 Received: from talho-ln2.nvidia.com (Not Verified[10.21.24.139]) by hqnvemgw02.nvidia.com with Trustwave SEG (v7, 5, 8, 10121) id ; Thu, 24 Jan 2019 09:04:08 -0800 From: Timo Alho To: , , , CC: , , Timo Alho Subject: [PATCH V3 4/4] dt-bindings: firmware: Add bindings for Tegra210 BPMP Date: Thu, 24 Jan 2019 19:03:55 +0200 Message-ID: <1548349435-1086-5-git-send-email-talho@nvidia.com> X-Mailer: git-send-email 2.7.4 In-Reply-To: <1548349435-1086-1-git-send-email-talho@nvidia.com> References: <1548349435-1086-1-git-send-email-talho@nvidia.com> MIME-Version: 1.0 DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=nvidia.com; s=n1; t=1548349431; bh=785DmzWjqc1nubJllLYM5ZGIriujs12Az85Oe2TLMGI=; h=X-PGP-Universal:From:To:CC:Subject:Date:Message-ID:X-Mailer: In-Reply-To:References:MIME-Version:Content-Type; b=BRENgec+PF6ik06M5jgE83ssnf3dV0QWnm7gzt9JXcsxOyRuAnkabTEmD+jNDiksi ZnoEXAjbAc4jcx1cmwbgZ3eIVax5oE0CyYHmCJgs9OGr6Ax8veI12jOwi1OtL10y0V UTctszxwj8PQ7xlqg3hrUltM5wBMgtJvVlP88fU41rOmxSwXYV7rO6qezXPWYA0rd0 GvO+O2SnaNsqPSuPISP8BPSCUBfbUPKLnmM66u5UEeF5DevH66D3r422slsw5Q5XjQ 21Mi72ktQV4fTODrqhveTdnz31MezuOSUp/nA43x/2yalVZ9uQGxbsyX0uU8HCG/9+ Z+zvWakhtSxYw== Sender: linux-tegra-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: linux-tegra@vger.kernel.org The BPMP is a specific processor in Tegra210 chip, which is designed for boot process handling, assisting in entering deep low power states (suspend to ram), and offloading DRAM memory clock scaling on some platforms. Signed-off-by: Timo Alho Reviewed-by: Rob Herring --- .../bindings/firmware/nvidia,tegra210-bpmp.txt | 36 ++++++++++++++++++++++ 1 file changed, 36 insertions(+) create mode 100644 Documentation/devicetree/bindings/firmware/nvidia,tegra210-bpmp.txt diff --git a/Documentation/devicetree/bindings/firmware/nvidia,tegra210-bpmp.txt b/Documentation/devicetree/bindings/firmware/nvidia,tegra210-bpmp.txt new file mode 100644 index 0000000..632d492 --- /dev/null +++ b/Documentation/devicetree/bindings/firmware/nvidia,tegra210-bpmp.txt @@ -0,0 +1,36 @@ +NVIDIA Tegra210 Boot and Power Management Processor (BPMP) + +The Boot and Power Management Processor (BPMP) is a co-processor found +in Tegra210 SoC. It is designed to handle the early stages of the boot +process as well as to assisting in entering deep low power state +(suspend to ram), and also offloading DRAM memory clock scaling on +some platforms. The binding document defines the resources that would +be used by the BPMP T210 firmware driver, which can create the +interprocessor communication (IPC) between the CPU and BPMP. + +Required properties: +- name : Should be bpmp +- compatible + Array of strings + One of: + - "nvidia,tegra210-bpmp" +- reg: physical base address and length for HW synchornization primitives + 1) base address and length to Tegra 'atomics' hardware + 2) base address and length to Tegra 'semaphore' hardware +- interrupts: specifies the interrupt number for receiving messages ("rx") + and for triggering messages ("tx") + +Optional properties: +- #clock-cells : Should be 1 for platforms where DRAM clock control is + offloaded to bpmp. + +Example: + +bpmp@70016000 { + compatible = "nvidia,tegra210-bpmp"; + reg = <0x0 0x70016000 0x0 0x2000 + 0x0 0x60001000 0x0 0x1000>; + interrupts = , + ; + interrupt-names = "tx", "rx"; +};