From patchwork Thu Jul 26 12:19:18 2018 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Aapo Vienamo X-Patchwork-Id: 949608 Return-Path: X-Original-To: incoming@patchwork.ozlabs.org Delivered-To: patchwork-incoming@bilbo.ozlabs.org Authentication-Results: ozlabs.org; spf=none (mailfrom) smtp.mailfrom=vger.kernel.org (client-ip=209.132.180.67; helo=vger.kernel.org; envelope-from=linux-tegra-owner@vger.kernel.org; receiver=) Authentication-Results: ozlabs.org; dmarc=fail (p=none dis=none) header.from=nvidia.com Received: from vger.kernel.org (vger.kernel.org [209.132.180.67]) by ozlabs.org (Postfix) with ESMTP id 41brlH6xNGz9ryl for ; Thu, 26 Jul 2018 22:20:11 +1000 (AEST) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1730589AbeGZNg2 (ORCPT ); Thu, 26 Jul 2018 09:36:28 -0400 Received: from hqemgate14.nvidia.com ([216.228.121.143]:16112 "EHLO hqemgate14.nvidia.com" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1730275AbeGZNg1 (ORCPT ); Thu, 26 Jul 2018 09:36:27 -0400 Received: from hqpgpgate101.nvidia.com (Not Verified[216.228.121.13]) by hqemgate14.nvidia.com (using TLS: TLSv1, AES128-SHA) id ; Thu, 26 Jul 2018 05:19:44 -0700 Received: from HQMAIL104.nvidia.com ([172.20.161.6]) by hqpgpgate101.nvidia.com (PGP Universal service); Thu, 26 Jul 2018 05:19:52 -0700 X-PGP-Universal: processed; by hqpgpgate101.nvidia.com on Thu, 26 Jul 2018 05:19:52 -0700 Received: from HQMAIL111.nvidia.com (172.20.187.18) by HQMAIL104.nvidia.com (172.18.146.11) with Microsoft SMTP Server (TLS) id 15.0.1347.2; Thu, 26 Jul 2018 12:19:52 +0000 Received: from HQMAIL105.nvidia.com (172.20.187.12) by HQMAIL111.nvidia.com (172.20.187.18) with Microsoft SMTP Server (TLS) id 15.0.1347.2; Thu, 26 Jul 2018 12:19:52 +0000 Received: from hqnvemgw01.nvidia.com (172.20.150.20) by HQMAIL105.nvidia.com (172.20.187.12) with Microsoft SMTP Server (TLS) id 15.0.1347.2 via Frontend Transport; Thu, 26 Jul 2018 12:19:52 +0000 Received: from dhcp-10-21-25-168.Nvidia.com (Not Verified[10.21.25.201]) by hqnvemgw01.nvidia.com with Trustwave SEG (v7, 5, 8, 10121) id ; Thu, 26 Jul 2018 05:19:51 -0700 From: Aapo Vienamo To: Ulf Hansson , Rob Herring , Mark Rutland , Thierry Reding , Jonathan Hunter , "Adrian Hunter" , Mikko Perttunen CC: , , , , Aapo Vienamo Subject: [PATCH v2 08/10] arm64: dts: tegra210-p2597: Remove no-1-8-v from sdmmc1 Date: Thu, 26 Jul 2018 15:19:18 +0300 Message-ID: <1532607560-11253-9-git-send-email-avienamo@nvidia.com> X-Mailer: git-send-email 2.7.4 In-Reply-To: <1532607560-11253-1-git-send-email-avienamo@nvidia.com> References: <1532607560-11253-1-git-send-email-avienamo@nvidia.com> X-NVConfidentiality: public MIME-Version: 1.0 Sender: linux-tegra-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: linux-tegra@vger.kernel.org Allow sdmmc1 to set the signaling voltage to 1.8 V in order to support faster signaling modes. Signed-off-by: Aapo Vienamo --- arch/arm64/boot/dts/nvidia/tegra210-p2597.dtsi | 1 - 1 file changed, 1 deletion(-) diff --git a/arch/arm64/boot/dts/nvidia/tegra210-p2597.dtsi b/arch/arm64/boot/dts/nvidia/tegra210-p2597.dtsi index 9d5a0e6..365726d 100644 --- a/arch/arm64/boot/dts/nvidia/tegra210-p2597.dtsi +++ b/arch/arm64/boot/dts/nvidia/tegra210-p2597.dtsi @@ -1452,7 +1452,6 @@ sdhci@700b0000 { status = "okay"; bus-width = <4>; - no-1-8-v; cd-gpios = <&gpio TEGRA_GPIO(Z, 1) GPIO_ACTIVE_LOW>;