From patchwork Wed Jul 11 14:39:24 2018 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Aapo Vienamo X-Patchwork-Id: 942532 Return-Path: X-Original-To: incoming@patchwork.ozlabs.org Delivered-To: patchwork-incoming@bilbo.ozlabs.org Authentication-Results: ozlabs.org; spf=none (mailfrom) smtp.mailfrom=vger.kernel.org (client-ip=209.132.180.67; helo=vger.kernel.org; envelope-from=linux-tegra-owner@vger.kernel.org; receiver=) Authentication-Results: ozlabs.org; dmarc=fail (p=none dis=none) header.from=nvidia.com Received: from vger.kernel.org (vger.kernel.org [209.132.180.67]) by ozlabs.org (Postfix) with ESMTP id 41QhYM5HC6zB4MQ for ; Thu, 12 Jul 2018 00:39:51 +1000 (AEST) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S2388787AbeGKOoT (ORCPT ); Wed, 11 Jul 2018 10:44:19 -0400 Received: from hqemgate16.nvidia.com ([216.228.121.65]:16897 "EHLO hqemgate16.nvidia.com" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S2388777AbeGKOoS (ORCPT ); Wed, 11 Jul 2018 10:44:18 -0400 Received: from hqpgpgate102.nvidia.com (Not Verified[216.228.121.13]) by hqemgate16.nvidia.com (using TLS: TLSv1, AES128-SHA) id ; Wed, 11 Jul 2018 07:39:33 -0700 Received: from HQMAIL104.nvidia.com ([172.20.161.6]) by hqpgpgate102.nvidia.com (PGP Universal service); Wed, 11 Jul 2018 07:39:34 -0700 X-PGP-Universal: processed; by hqpgpgate102.nvidia.com on Wed, 11 Jul 2018 07:39:34 -0700 Received: from HQMAIL109.nvidia.com (172.20.187.15) by HQMAIL104.nvidia.com (172.18.146.11) with Microsoft SMTP Server (TLS) id 15.0.1347.2; Wed, 11 Jul 2018 14:39:37 +0000 Received: from HQMAIL102.nvidia.com (172.18.146.10) by HQMAIL109.nvidia.com (172.20.187.15) with Microsoft SMTP Server (TLS) id 15.0.1347.2; Wed, 11 Jul 2018 14:39:37 +0000 Received: from hqnvemgw02.nvidia.com (172.16.227.111) by HQMAIL102.nvidia.com (172.18.146.10) with Microsoft SMTP Server (TLS) id 15.0.1347.2 via Frontend Transport; Wed, 11 Jul 2018 14:39:37 +0000 Received: from dhcp-10-21-25-168.Nvidia.com (Not Verified[10.21.25.201]) by hqnvemgw02.nvidia.com with Trustwave SEG (v7, 5, 8, 10121) id ; Wed, 11 Jul 2018 07:39:37 -0700 From: Aapo Vienamo To: Peter De Schrijver CC: Prashant Gaikwad , Michael Turquette , Stephen Boyd , Thierry Reding , Jonathan Hunter , , , , Aapo Vienamo Subject: [PATCH v5 3/4] clk: tegra: Add sdmmc mux divider clock Date: Wed, 11 Jul 2018 17:39:24 +0300 Message-ID: <1531319965-19689-4-git-send-email-avienamo@nvidia.com> X-Mailer: git-send-email 2.7.4 In-Reply-To: <1531319965-19689-1-git-send-email-avienamo@nvidia.com> References: <1531319965-19689-1-git-send-email-avienamo@nvidia.com> X-NVConfidentiality: public MIME-Version: 1.0 Sender: linux-tegra-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: linux-tegra@vger.kernel.org From: Peter De-Schrijver Add a clock type to model the sdmmc switch divider clocks which have paths to source clocks bypassing the divider (Low Jitter paths). These are handled by selecting the lj path when the divider is 1 (ie the rate is the parent rate), otherwise the normal path with divider will be selected. Otherwise this clock behaves as a normal peripheral clock. Signed-off-by: Peter De-Schrijver Signed-off-by: Aapo Vienamo Acked-by: Peter De Schrijver --- drivers/clk/tegra/Makefile | 1 + drivers/clk/tegra/clk-sdmmc-mux.c | 249 ++++++++++++++++++++++++++++++++++++++ drivers/clk/tegra/clk.h | 26 ++++ 3 files changed, 276 insertions(+) create mode 100644 drivers/clk/tegra/clk-sdmmc-mux.c diff --git a/drivers/clk/tegra/Makefile b/drivers/clk/tegra/Makefile index c79319d..8975f88 100644 --- a/drivers/clk/tegra/Makefile +++ b/drivers/clk/tegra/Makefile @@ -8,6 +8,7 @@ obj-y += clk-periph-fixed.o obj-y += clk-periph-gate.o obj-y += clk-pll.o obj-y += clk-pll-out.o +obj-y += clk-sdmmc-mux.o obj-y += clk-super.o obj-y += clk-tegra-audio.o obj-y += clk-tegra-periph.o diff --git a/drivers/clk/tegra/clk-sdmmc-mux.c b/drivers/clk/tegra/clk-sdmmc-mux.c new file mode 100644 index 0000000..9566754 --- /dev/null +++ b/drivers/clk/tegra/clk-sdmmc-mux.c @@ -0,0 +1,249 @@ +// SPDX-License-Identifier: GPL-2.0 +/* + * Copyright (c) 2018 NVIDIA CORPORATION. All rights reserved. + * + * based on clk-mux.c + * + * Copyright (C) 2011 Sascha Hauer, Pengutronix + * Copyright (C) 2011 Richard Zhao, Linaro + * Copyright (C) 2011-2012 Mike Turquette, Linaro Ltd + * + */ + +#include +#include +#include + +#include "clk.h" + +#define DIV_MASK GENMASK(7, 0) +#define MUX_SHIFT 29 +#define MUX_MASK GENMASK(MUX_SHIFT + 2, MUX_SHIFT) + +#define get_max_div(d) DIV_MASK +#define get_div_field(val) ((val) & DIV_MASK) +#define get_mux_field(val) (((val) & MUX_MASK) >> MUX_SHIFT) + +static const char * const mux_sdmmc_parents[] = { + "pll_p", "pll_c4_out2", "pll_c4_out0", "pll_c4_out1", "clk_m" +}; + +static const u8 mux_lj_idx[] = { + [0] = 0, [1] = 1, [2] = 2, [3] = 5, [4] = 6 +}; + +static const u8 mux_non_lj_idx[] = { + [0] = 0, [1] = 3, [2] = 7, [3] = 4, [4] = 6 +}; + +static u8 clk_sdmmc_mux_get_parent(struct clk_hw *hw) +{ + struct tegra_sdmmc_mux *sdmmc_mux = to_clk_sdmmc_mux(hw); + int num_parents, i; + u32 src, val; + const u8 *mux_idx; + + num_parents = clk_hw_get_num_parents(hw); + + val = readl_relaxed(sdmmc_mux->reg); + src = get_mux_field(val); + if (get_div_field(val)) + mux_idx = mux_non_lj_idx; + else + mux_idx = mux_lj_idx; + + for (i = 0; i < num_parents; i++) { + if (mux_idx[i] == src) + return i; + } + + WARN(1, "Unknown parent selector %d\n", src); + + return 0; +} + +static int clk_sdmmc_mux_set_parent(struct clk_hw *hw, u8 index) +{ + struct tegra_sdmmc_mux *sdmmc_mux = to_clk_sdmmc_mux(hw); + u32 val; + + + val = readl_relaxed(sdmmc_mux->reg); + if (get_div_field(val)) + index = mux_non_lj_idx[index]; + else + index = mux_lj_idx[index]; + + val &= ~MUX_MASK; + val |= index << MUX_SHIFT; + + writel(val, sdmmc_mux->reg); + + return 0; +} + +static unsigned long clk_sdmmc_mux_recalc_rate(struct clk_hw *hw, + unsigned long parent_rate) +{ + struct tegra_sdmmc_mux *sdmmc_mux = to_clk_sdmmc_mux(hw); + u32 val; + int div, mul; + u64 rate = parent_rate; + + val = readl_relaxed(sdmmc_mux->reg); + div = get_div_field(val); + + mul = 2; + div += mul; + + rate *= mul; + rate += div - 1; + do_div(rate, div); + + return rate; +} + +static int clk_sdmmc_mux_determine_rate(struct clk_hw *hw, + struct clk_rate_request *req) +{ + struct tegra_sdmmc_mux *sdmmc_mux = to_clk_sdmmc_mux(hw); + int div, mul; + unsigned long output_rate = req->best_parent_rate; + + req->rate = max(req->rate, req->min_rate); + req->rate = min(req->rate, req->max_rate); + + if (!req->rate) + return output_rate; + + div = div_frac_get(req->rate, output_rate, 8, 1, sdmmc_mux->div_flags); + if (div < 0) + div = 0; + + mul = 2; + if (sdmmc_mux->div_flags & TEGRA_DIVIDER_ROUND_UP) + req->rate = DIV_ROUND_UP(output_rate * mul, div + mul); + else + req->rate = output_rate * mul / (div + mul); + + return 0; +} + +static int clk_sdmmc_mux_set_rate(struct clk_hw *hw, unsigned long rate, + unsigned long parent_rate) +{ + struct tegra_sdmmc_mux *sdmmc_mux = to_clk_sdmmc_mux(hw); + int div; + unsigned long flags = 0; + u32 val; + u8 src; + + div = div_frac_get(rate, parent_rate, 8, 1, sdmmc_mux->div_flags); + if (div < 0) + return div; + + if (sdmmc_mux->lock) + spin_lock_irqsave(sdmmc_mux->lock, flags); + + src = clk_sdmmc_mux_get_parent(hw); + if (div) + src = mux_non_lj_idx[src]; + else + src = mux_lj_idx[src]; + + val = src << MUX_SHIFT; + val |= div; + writel(val, sdmmc_mux->reg); + fence_udelay(2, sdmmc_mux->reg); + + if (sdmmc_mux->lock) + spin_unlock_irqrestore(sdmmc_mux->lock, flags); + + return 0; +} + +static int clk_sdmmc_mux_is_enabled(struct clk_hw *hw) +{ + struct tegra_sdmmc_mux *sdmmc_mux = to_clk_sdmmc_mux(hw); + const struct clk_ops *gate_ops = sdmmc_mux->gate_ops; + struct clk_hw *gate_hw = &sdmmc_mux->gate.hw; + + __clk_hw_set_clk(gate_hw, hw); + + return gate_ops->is_enabled(gate_hw); +} + +static int clk_sdmmc_mux_enable(struct clk_hw *hw) +{ + struct tegra_sdmmc_mux *sdmmc_mux = to_clk_sdmmc_mux(hw); + const struct clk_ops *gate_ops = sdmmc_mux->gate_ops; + struct clk_hw *gate_hw = &sdmmc_mux->gate.hw; + + __clk_hw_set_clk(gate_hw, hw); + + return gate_ops->enable(gate_hw); +} + +static void clk_sdmmc_mux_disable(struct clk_hw *hw) +{ + struct tegra_sdmmc_mux *sdmmc_mux = to_clk_sdmmc_mux(hw); + const struct clk_ops *gate_ops = sdmmc_mux->gate_ops; + struct clk_hw *gate_hw = &sdmmc_mux->gate.hw; + + gate_ops->disable(gate_hw); +} + +static const struct clk_ops tegra_clk_sdmmc_mux_ops = { + .get_parent = clk_sdmmc_mux_get_parent, + .set_parent = clk_sdmmc_mux_set_parent, + .determine_rate = clk_sdmmc_mux_determine_rate, + .recalc_rate = clk_sdmmc_mux_recalc_rate, + .set_rate = clk_sdmmc_mux_set_rate, + .is_enabled = clk_sdmmc_mux_is_enabled, + .enable = clk_sdmmc_mux_enable, + .disable = clk_sdmmc_mux_disable, +}; + +struct clk *tegra_clk_register_sdmmc_mux_div(const char *name, + void __iomem *clk_base, u32 offset, u32 clk_num, u8 div_flags, + unsigned long flags, void *lock) +{ + struct clk *clk; + struct clk_init_data init; + const struct tegra_clk_periph_regs *bank; + struct tegra_sdmmc_mux *sdmmc_mux; + + init.ops = &tegra_clk_sdmmc_mux_ops; + init.name = name; + init.flags = flags; + init.parent_names = mux_sdmmc_parents; + init.num_parents = ARRAY_SIZE(mux_sdmmc_parents); + + bank = get_reg_bank(clk_num); + if (!bank) + return ERR_PTR(-EINVAL); + + sdmmc_mux = kzalloc(sizeof(*sdmmc_mux), GFP_KERNEL); + if (!sdmmc_mux) + return ERR_PTR(-ENOMEM); + + /* Data in .init is copied by clk_register(), so stack variable OK */ + sdmmc_mux->hw.init = &init; + sdmmc_mux->reg = clk_base + offset; + sdmmc_mux->lock = lock; + sdmmc_mux->gate.clk_base = clk_base; + sdmmc_mux->gate.regs = bank; + sdmmc_mux->gate.enable_refcnt = periph_clk_enb_refcnt; + sdmmc_mux->gate.clk_num = clk_num; + sdmmc_mux->gate.flags = TEGRA_PERIPH_ON_APB; + sdmmc_mux->div_flags = div_flags; + sdmmc_mux->gate_ops = &tegra_clk_periph_gate_ops; + + clk = clk_register(NULL, &sdmmc_mux->hw); + if (IS_ERR(clk)) + return clk; + + sdmmc_mux->gate.hw.clk = clk; + + return clk; +} diff --git a/drivers/clk/tegra/clk.h b/drivers/clk/tegra/clk.h index c733841..d2c3a01 100644 --- a/drivers/clk/tegra/clk.h +++ b/drivers/clk/tegra/clk.h @@ -706,6 +706,32 @@ struct clk *tegra_clk_register_super_clk(const char *name, const char * const *parent_names, u8 num_parents, unsigned long flags, void __iomem *reg, u8 clk_super_flags, spinlock_t *lock); + +/** + * struct tegra_sdmmc_mux - switch divider with Low Jitter inputs for SDMMC + * + * @hw: handle between common and hardware-specific interfaces + * @reg: register controlling mux and divider + * @flags: hardware-specific flags + * @lock: optional register lock + * @gate: gate clock + * @gate_ops: gate clock ops + */ +struct tegra_sdmmc_mux { + struct clk_hw hw; + void __iomem *reg; + spinlock_t *lock; + const struct clk_ops *gate_ops; + struct tegra_clk_periph_gate gate; + u8 div_flags; +}; + +#define to_clk_sdmmc_mux(_hw) container_of(_hw, struct tegra_sdmmc_mux, hw) + +struct clk *tegra_clk_register_sdmmc_mux_div(const char *name, + void __iomem *clk_base, u32 offset, u32 clk_num, u8 div_flags, + unsigned long flags, void *lock); + /** * struct clk_init_table - clock initialization table * @clk_id: clock id as mentioned in device tree bindings