From patchwork Mon Jan 8 04:54:38 2018 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Mikko Perttunen X-Patchwork-Id: 856703 Return-Path: X-Original-To: incoming@patchwork.ozlabs.org Delivered-To: patchwork-incoming@bilbo.ozlabs.org Authentication-Results: ozlabs.org; spf=none (mailfrom) smtp.mailfrom=vger.kernel.org (client-ip=209.132.180.67; helo=vger.kernel.org; envelope-from=linux-tegra-owner@vger.kernel.org; receiver=) Received: from vger.kernel.org (vger.kernel.org [209.132.180.67]) by ozlabs.org (Postfix) with ESMTP id 3zFNJw0P47z9s7f for ; Mon, 8 Jan 2018 15:56:16 +1100 (AEDT) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1755533AbeAHE4E (ORCPT ); Sun, 7 Jan 2018 23:56:04 -0500 Received: from hqemgate16.nvidia.com ([216.228.121.65]:5381 "EHLO hqemgate16.nvidia.com" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1755504AbeAHEzp (ORCPT ); Sun, 7 Jan 2018 23:55:45 -0500 Received: from hqpgpgate101.nvidia.com (Not Verified[216.228.121.13]) by hqemgate16.nvidia.com id ; Sun, 07 Jan 2018 20:55:58 -0800 Received: from HQMAIL103.nvidia.com ([172.20.161.6]) by hqpgpgate101.nvidia.com (PGP Universal service); Sun, 07 Jan 2018 20:55:45 -0800 X-PGP-Universal: processed; by hqpgpgate101.nvidia.com on Sun, 07 Jan 2018 20:55:45 -0800 Received: from HQMAIL111.nvidia.com (172.20.187.18) by HQMAIL103.nvidia.com (172.20.187.11) with Microsoft SMTP Server (TLS) id 15.0.1347.2; Mon, 8 Jan 2018 04:55:44 +0000 Received: from HQMAIL107.nvidia.com (172.20.187.13) by HQMAIL111.nvidia.com (172.20.187.18) with Microsoft SMTP Server (TLS) id 15.0.1347.2; Mon, 8 Jan 2018 04:55:44 +0000 Received: from hqnvemgw01.nvidia.com (172.20.150.20) by HQMAIL107.nvidia.com (172.20.187.13) with Microsoft SMTP Server id 15.0.1347.2 via Frontend Transport; Mon, 8 Jan 2018 04:55:44 +0000 Received: from mperttunen-lnx.Nvidia.com (Not Verified[10.21.26.144]) by hqnvemgw01.nvidia.com with Trustwave SEG (v7, 5, 8, 10121) id ; Sun, 07 Jan 2018 20:55:44 -0800 From: Mikko Perttunen To: , , , CC: , , , , , Mikko Perttunen Subject: [PATCH 6/6] arm64: tegra: Add device tree for the Tegra194 P2972-0000 board Date: Mon, 8 Jan 2018 06:54:38 +0200 Message-ID: <1515387278-29777-7-git-send-email-mperttunen@nvidia.com> X-Mailer: git-send-email 2.1.4 In-Reply-To: <1515387278-29777-1-git-send-email-mperttunen@nvidia.com> References: <1515387278-29777-1-git-send-email-mperttunen@nvidia.com> X-NVConfidentiality: public MIME-Version: 1.0 Sender: linux-tegra-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: linux-tegra@vger.kernel.org Add device tree files for the Tegra194 P2972-0000 development board. The board consists of the P2888 compute module and the P2822 baseboard. Signed-off-by: Mikko Perttunen --- arch/arm64/boot/dts/nvidia/Makefile | 1 + arch/arm64/boot/dts/nvidia/tegra194-p2888.dtsi | 246 +++++++++++++++++++++ arch/arm64/boot/dts/nvidia/tegra194-p2972-0000.dts | 14 ++ 3 files changed, 261 insertions(+) create mode 100644 arch/arm64/boot/dts/nvidia/tegra194-p2888.dtsi create mode 100644 arch/arm64/boot/dts/nvidia/tegra194-p2972-0000.dts diff --git a/arch/arm64/boot/dts/nvidia/Makefile b/arch/arm64/boot/dts/nvidia/Makefile index 676aa2f238d1..7c13d7df484e 100644 --- a/arch/arm64/boot/dts/nvidia/Makefile +++ b/arch/arm64/boot/dts/nvidia/Makefile @@ -5,3 +5,4 @@ dtb-$(CONFIG_ARCH_TEGRA_210_SOC) += tegra210-p2371-2180.dtb dtb-$(CONFIG_ARCH_TEGRA_210_SOC) += tegra210-p2571.dtb dtb-$(CONFIG_ARCH_TEGRA_210_SOC) += tegra210-smaug.dtb dtb-$(CONFIG_ARCH_TEGRA_186_SOC) += tegra186-p2771-0000.dtb +dtb-$(CONFIG_ARCH_TEGRA_194_SOC) += tegra194-p2972-0000.dtb diff --git a/arch/arm64/boot/dts/nvidia/tegra194-p2888.dtsi b/arch/arm64/boot/dts/nvidia/tegra194-p2888.dtsi new file mode 100644 index 000000000000..5b337f883d2c --- /dev/null +++ b/arch/arm64/boot/dts/nvidia/tegra194-p2888.dtsi @@ -0,0 +1,246 @@ +// SPDX-License-Identifier: GPL-2.0 +#include "tegra194.dtsi" + +#include + +/ { + model = "NVIDIA Tegra194 P2888 Processor Module"; + compatible = "nvidia,p2888", "nvidia,tegra194"; + + aliases { + sdhci0 = "/sdhci@3460000"; + sdhci1 = "/sdhci@3400000"; + serial0 = &uartc; + i2c0 = "/bpmp/i2c"; + i2c1 = "/i2c@3160000"; + i2c2 = "/i2c@c240000"; + i2c3 = "/i2c@3180000"; + i2c4 = "/i2c@3190000"; + i2c5 = "/i2c@31c0000"; + i2c6 = "/i2c@c250000"; + i2c7 = "/i2c@31e0000"; + }; + + chosen { + bootargs = "earlycon console=ttyS0,115200n8"; + stdout-path = "serial0:115200n8"; + }; + + serial@c280000 { + status = "okay"; + }; + + /* SDMMC1 (SD/MMC) */ + sdhci@3400000 { +/* + cd-gpios = <&gpio TEGRA194_MAIN_GPIO(A, 0) GPIO_ACTIVE_LOW>; +*/ + }; + + /* SDMMC4 (eMMC) */ + sdhci@3460000 { + status = "okay"; + bus-width = <8>; + non-removable; + + vqmmc-supply = <&vdd_1v8ls>; + vmmc-supply = <&vdd_emmc_3v3>; + }; + + pmc@c360000 { + nvidia,invert-interrupt; + }; + + bpmp { + i2c { + status = "okay"; + + pmic: pmic@3c { + compatible = "maxim,max20024"; + reg = <0x3c>; + + interrupts = ; + #interrupt-cells = <2>; + interrupt-controller; + + #gpio-cells = <2>; + gpio-controller; + + pinctrl-names = "default"; + pinctrl-0 = <&max20024_default>; + + max20024_default: pinmux { + gpio0 { + pins = "gpio0"; + function = "gpio"; + }; + + gpio1 { + pins = "gpio1"; + function = "fps-out"; + maxim,active-fps-source = ; + }; + + gpio2 { + pins = "gpio2"; + function = "fps-out"; + maxim,active-fps-source = ; + }; + + gpio3 { + pins = "gpio3"; + function = "fps-out"; + maxim,active-fps-source = ; + }; + + gpio4 { + pins = "gpio4"; + function = "32k-out1"; + drive-push-pull = <1>; + }; + + gpio6 { + pins = "gpio6"; + function = "gpio"; + drive-push-pull = <1>; + }; + + gpio7 { + pins = "gpio7"; + function = "gpio"; + drive-push-pull = <0>; + }; + }; + + fps { + fps0 { + maxim,fps-event-source = ; + maxim,shutdown-fps-time-period-us = <640>; + }; + + fps1 { + maxim,fps-event-source = ; + maxim,shutdown-fps-time-period-us = <640>; + maxim,device-state-on-disabled-event = ; + }; + + fps2 { + maxim,fps-event-source = ; + maxim,shutdown-fps-time-period-us = <640>; + }; + }; + + regulators { + in-sd0-supply = <&vdd_5v0_sys>; + in-sd1-supply = <&vdd_5v0_sys>; + in-sd2-supply = <&vdd_5v0_sys>; + in-sd3-supply = <&vdd_5v0_sys>; + in-sd4-supply = <&vdd_5v0_sys>; + + in-ldo0-1-supply = <&vdd_5v0_sys>; + in-ldo2-supply = <&vdd_5v0_sys>; + in-ldo3-5-supply = <&vdd_5v0_sys>; + in-ldo4-6-supply = <&vdd_5v0_sys>; + in-ldo7-8-supply = <&vdd_1v8ls>; + + sd0 { + regulator-name = "VDD_1V0"; + regulator-min-microvolt = <1000000>; + regulator-max-microvolt = <1000000>; + regulator-always-on; + regulator-boot-on; + }; + + sd1 { + regulator-name = "VDD_1V8HS"; + regulator-min-microvolt = <1800000>; + regulator-max-microvolt = <1800000>; + regulator-always-on; + regulator-boot-on; + }; + + vdd_1v8ls: sd2 { + regulator-name = "VDD_1V8LS"; + regulator-min-microvolt = <1800000>; + regulator-max-microvolt = <1800000>; + regulator-always-on; + regulator-boot-on; + }; + + sd3 { + regulator-name = "VDD_1V8AO"; + regulator-min-microvolt = <1800000>; + regulator-max-microvolt = <1800000>; + regulator-always-on; + regulator-boot-on; + }; + + sd4 { + regulator-name = "VDD_DDR_1V1"; + regulator-min-microvolt = <1100000>; + regulator-max-microvolt = <1100000>; + regulator-always-on; + regulator-boot-on; + }; + + ldo0 { + regulator-name = "VDD_RTC"; + regulator-min-microvolt = <800000>; + regulator-max-microvolt = <800000>; + regulator-always-on; + regulator-boot-on; + }; + + ldo2 { + regulator-name = "VDD_AO_3V3"; + regulator-min-microvolt = <3300000>; + regulator-max-microvolt = <3300000>; + regulator-always-on; + regulator-boot-on; + }; + + vdd_emmc_3v3: ldo3 { + regulator-name = "VDD_EMMC_3V3"; + regulator-min-microvolt = <3300000>; + regulator-max-microvolt = <3300000>; + }; + + ldo5 { + regulator-name = "VDD_USB_3V3"; + regulator-min-microvolt = <3300000>; + regulator-max-microvolt = <3300000>; + }; + + ldo6 { + regulator-name = "VDD_SDIO_3V3"; + regulator-min-microvolt = <3300000>; + regulator-max-microvolt = <3300000>; + }; + + ldo7 { + regulator-name = "VDD_CSI_1V2"; + regulator-min-microvolt = <1200000>; + regulator-max-microvolt = <1200000>; + }; + }; + }; + }; + }; + + regulators { + compatible = "simple-bus"; + #address-cells = <1>; + #size-cells = <0>; + + vdd_5v0_sys: regulator@0 { + compatible = "regulator-fixed"; + reg = <0>; + + regulator-name = "VIN_SYS_5V0"; + regulator-min-microvolt = <5000000>; + regulator-max-microvolt = <5000000>; + regulator-always-on; + regulator-boot-on; + }; + }; +}; diff --git a/arch/arm64/boot/dts/nvidia/tegra194-p2972-0000.dts b/arch/arm64/boot/dts/nvidia/tegra194-p2972-0000.dts new file mode 100644 index 000000000000..9f0b463ee5f7 --- /dev/null +++ b/arch/arm64/boot/dts/nvidia/tegra194-p2972-0000.dts @@ -0,0 +1,14 @@ +// SPDX-License-Identifier: GPL-2.0 +/dts-v1/; + +#include "tegra194-p2888.dtsi" + +/ { + model = "NVIDIA Tegra194 P2972-0000 Development Board"; + compatible = "nvidia,p2972-0000", "nvidia,tegra194"; + + /* SDMMC1 (SD/MMC) */ + sdhci@3400000 { + status = "okay"; + }; +};