From patchwork Tue Jun 6 08:59:33 2017 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Jon Hunter X-Patchwork-Id: 771722 Return-Path: X-Original-To: incoming@patchwork.ozlabs.org Delivered-To: patchwork-incoming@bilbo.ozlabs.org Received: from vger.kernel.org (vger.kernel.org [209.132.180.67]) by ozlabs.org (Postfix) with ESMTP id 3whlxW09sLz9s0g for ; Tue, 6 Jun 2017 18:59:43 +1000 (AEST) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1751330AbdFFI7l (ORCPT ); Tue, 6 Jun 2017 04:59:41 -0400 Received: from hqemgate14.nvidia.com ([216.228.121.143]:16155 "EHLO hqemgate14.nvidia.com" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1751246AbdFFI7l (ORCPT ); Tue, 6 Jun 2017 04:59:41 -0400 Received: from hqpgpgate102.nvidia.com (Not Verified[216.228.121.13]) by hqemgate14.nvidia.com id ; Tue, 06 Jun 2017 01:59:41 -0700 Received: from HQMAIL101.nvidia.com ([172.20.13.39]) by hqpgpgate102.nvidia.com (PGP Universal service); Tue, 06 Jun 2017 01:59:40 -0700 X-PGP-Universal: processed; by hqpgpgate102.nvidia.com on Tue, 06 Jun 2017 01:59:40 -0700 Received: from HQMAIL101.nvidia.com (172.20.187.10) by HQMAIL101.nvidia.com (172.20.187.10) with Microsoft SMTP Server (TLS) id 15.0.1263.5; Tue, 6 Jun 2017 08:59:40 +0000 Received: from hqnvemgw01.nvidia.com (172.20.150.20) by HQMAIL101.nvidia.com (172.20.187.10) with Microsoft SMTP Server id 15.0.1263.5 via Frontend Transport; Tue, 6 Jun 2017 08:59:40 +0000 Received: from goldfinger.nvidia.com (Not Verified[10.26.11.196]) by hqnvemgw01.nvidia.com with Trustwave SEG (v7, 5, 5, 8150) id ; Tue, 06 Jun 2017 01:59:39 -0700 From: Jon Hunter To: Laxman Dewangan , Vinod Koul CC: Thierry Reding , , , Jon Hunter Subject: [PATCH] dmaengine: tegra-apb: Really fix runtime-pm usage Date: Tue, 6 Jun 2017 09:59:33 +0100 Message-ID: <1496739573-26565-1-git-send-email-jonathanh@nvidia.com> X-Mailer: git-send-email 2.7.4 X-NVConfidentiality: public MIME-Version: 1.0 Sender: linux-tegra-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: linux-tegra@vger.kernel.org Commit edd3bdbe9db1 ("dmaengine: tegra-apb: Correct runtime-pm usage") added pm_runtime_get/put() calls to the tegra-apb DMA system suspend callbacks. Runtime PM is disabled during system suspend and so these APIs cannot be used. Fix the suspend handling for the tegra-apb DMA by moving the save and restore of the DMA register context into the runtime PM suspend and resume callbacks, and then use the pm_runtime_force_suspend/resume() APIs to invoke the runtime PM callbacks during system suspend. Fixes: edd3bdbe9db1 ("dmaengine: tegra-apb: Correct runtime-pm usage") Signed-off-by: Jon Hunter --- drivers/dma/tegra20-apb-dma.c | 57 +++++++++++++++---------------------------- 1 file changed, 19 insertions(+), 38 deletions(-) diff --git a/drivers/dma/tegra20-apb-dma.c b/drivers/dma/tegra20-apb-dma.c index 3722b9d8d9fe..5c3ddd61dc3b 100644 --- a/drivers/dma/tegra20-apb-dma.c +++ b/drivers/dma/tegra20-apb-dma.c @@ -1494,35 +1494,7 @@ static int tegra_dma_remove(struct platform_device *pdev) static int tegra_dma_runtime_suspend(struct device *dev) { struct tegra_dma *tdma = dev_get_drvdata(dev); - - clk_disable_unprepare(tdma->dma_clk); - return 0; -} - -static int tegra_dma_runtime_resume(struct device *dev) -{ - struct tegra_dma *tdma = dev_get_drvdata(dev); - int ret; - - ret = clk_prepare_enable(tdma->dma_clk); - if (ret < 0) { - dev_err(dev, "clk_enable failed: %d\n", ret); - return ret; - } - return 0; -} - -#ifdef CONFIG_PM_SLEEP -static int tegra_dma_pm_suspend(struct device *dev) -{ - struct tegra_dma *tdma = dev_get_drvdata(dev); int i; - int ret; - - /* Enable clock before accessing register */ - ret = pm_runtime_get_sync(dev); - if (ret < 0) - return ret; tdma->reg_gen = tdma_read(tdma, TEGRA_APBDMA_GENERAL); for (i = 0; i < tdma->chip_data->nr_channels; i++) { @@ -1543,21 +1515,21 @@ static int tegra_dma_pm_suspend(struct device *dev) TEGRA_APBDMA_CHAN_WCOUNT); } - /* Disable clock */ - pm_runtime_put(dev); + clk_disable_unprepare(tdma->dma_clk); + return 0; } -static int tegra_dma_pm_resume(struct device *dev) +static int tegra_dma_runtime_resume(struct device *dev) { struct tegra_dma *tdma = dev_get_drvdata(dev); - int i; - int ret; + int i, ret; - /* Enable clock before accessing register */ - ret = pm_runtime_get_sync(dev); - if (ret < 0) + ret = clk_prepare_enable(tdma->dma_clk); + if (ret < 0) { + dev_err(dev, "clk_enable failed: %d\n", ret); return ret; + } tdma_write(tdma, TEGRA_APBDMA_GENERAL, tdma->reg_gen); tdma_write(tdma, TEGRA_APBDMA_CONTROL, 0); @@ -1582,10 +1554,19 @@ static int tegra_dma_pm_resume(struct device *dev) (ch_reg->csr & ~TEGRA_APBDMA_CSR_ENB)); } - /* Disable clock */ - pm_runtime_put(dev); return 0; } + +#ifdef CONFIG_PM_SLEEP +static int tegra_dma_pm_suspend(struct device *dev) +{ + return pm_runtime_force_suspend(dev); +} + +static int tegra_dma_pm_resume(struct device *dev) +{ + return pm_runtime_force_resume(dev); +} #endif static const struct dev_pm_ops tegra_dma_dev_pm_ops = {