From patchwork Wed Mar 15 13:31:51 2017 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Jon Hunter X-Patchwork-Id: 739223 Return-Path: X-Original-To: incoming@patchwork.ozlabs.org Delivered-To: patchwork-incoming@bilbo.ozlabs.org Received: from vger.kernel.org (vger.kernel.org [209.132.180.67]) by ozlabs.org (Postfix) with ESMTP id 3vjswR2Blsz9ryr for ; Thu, 16 Mar 2017 00:32:23 +1100 (AEDT) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1753624AbdCONcV (ORCPT ); Wed, 15 Mar 2017 09:32:21 -0400 Received: from hqemgate16.nvidia.com ([216.228.121.65]:4136 "EHLO hqemgate16.nvidia.com" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1752117AbdCONcK (ORCPT ); Wed, 15 Mar 2017 09:32:10 -0400 Received: from hqpgpgate101.nvidia.com (Not Verified[216.228.121.13]) by hqemgate16.nvidia.com id ; Wed, 15 Mar 2017 06:32:01 -0700 Received: from HQMAIL101.nvidia.com ([172.20.13.39]) by hqpgpgate101.nvidia.com (PGP Universal service); Wed, 15 Mar 2017 06:32:09 -0700 X-PGP-Universal: processed; by hqpgpgate101.nvidia.com on Wed, 15 Mar 2017 06:32:09 -0700 Received: from HQMAIL111.nvidia.com (172.20.187.18) by HQMAIL101.nvidia.com (172.20.187.10) with Microsoft SMTP Server (TLS) id 15.0.1263.5; Wed, 15 Mar 2017 13:32:08 +0000 Received: from HQMAIL101.nvidia.com (172.20.187.10) by HQMAIL111.nvidia.com (172.20.187.18) with Microsoft SMTP Server (TLS) id 15.0.1263.5; Wed, 15 Mar 2017 13:32:08 +0000 Received: from hqnvemgw02.nvidia.com (172.16.227.111) by HQMAIL101.nvidia.com (172.20.187.10) with Microsoft SMTP Server id 15.0.1263.5 via Frontend Transport; Wed, 15 Mar 2017 13:32:08 +0000 Received: from goldfinger.nvidia.com (Not Verified[10.21.132.151]) by hqnvemgw02.nvidia.com with Trustwave SEG (v7, 5, 5, 8150) id ; Wed, 15 Mar 2017 06:32:08 -0700 From: Jon Hunter To: Thierry Reding CC: Russell King , Rob Herring , Mark Rutland , , , , Jon Hunter Subject: [PATCH 1/5] ARM: tegra: WARN if flowctrl is not supported Date: Wed, 15 Mar 2017 13:31:51 +0000 Message-ID: <1489584715-23138-2-git-send-email-jonathanh@nvidia.com> X-Mailer: git-send-email 2.7.4 In-Reply-To: <1489584715-23138-1-git-send-email-jonathanh@nvidia.com> References: <1489584715-23138-1-git-send-email-jonathanh@nvidia.com> X-NVConfidentiality: public MIME-Version: 1.0 Sender: linux-tegra-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: linux-tegra@vger.kernel.org If we fail to map the IO space for the Tegra flowctrl module in tegra_flowctrl_init(), then if any of the public APIs for the Tegra flowctrl driver are called we still still attempt to access the hardware. Fix this by only accessing the hardware if the 'tegra_flowctrl_base' address has not been setup correctly and warn if we attempt to access the hardware when it has not. Signed-off-by: Jon Hunter --- arch/arm/mach-tegra/flowctrl.c | 6 ++++++ 1 file changed, 6 insertions(+) diff --git a/arch/arm/mach-tegra/flowctrl.c b/arch/arm/mach-tegra/flowctrl.c index 475e783992fd..40b15e39f849 100644 --- a/arch/arm/mach-tegra/flowctrl.c +++ b/arch/arm/mach-tegra/flowctrl.c @@ -47,6 +47,9 @@ static void __iomem *tegra_flowctrl_base; static void flowctrl_update(u8 offset, u32 value) { + if (WARN_ONCE(!tegra_flowctrl_base, "Tegra flowctrl not supported!")) + return; + writel(value, tegra_flowctrl_base + offset); /* ensure the update has reached the flow controller */ @@ -58,6 +61,9 @@ u32 flowctrl_read_cpu_csr(unsigned int cpuid) { u8 offset = flowctrl_offset_cpu_csr[cpuid]; + if (WARN_ONCE(!tegra_flowctrl_base, "Tegra flowctrl not supported!")) + return 0; + return readl(tegra_flowctrl_base + offset); }