From patchwork Tue Aug 30 19:11:17 2016 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Shardar Shariff Md X-Patchwork-Id: 664278 X-Patchwork-Delegate: jonathanh@nvidia.com Return-Path: X-Original-To: incoming@patchwork.ozlabs.org Delivered-To: patchwork-incoming@bilbo.ozlabs.org Received: from vger.kernel.org (vger.kernel.org [209.132.180.67]) by ozlabs.org (Postfix) with ESMTP id 3sNynm1wgxz9sBX for ; Wed, 31 Aug 2016 05:12:28 +1000 (AEST) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1751372AbcH3TLm (ORCPT ); Tue, 30 Aug 2016 15:11:42 -0400 Received: from hqemgate15.nvidia.com ([216.228.121.64]:2413 "EHLO hqemgate15.nvidia.com" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1750825AbcH3TLk (ORCPT ); Tue, 30 Aug 2016 15:11:40 -0400 Received: from hqnvupgp07.nvidia.com (Not Verified[216.228.121.13]) by hqemgate15.nvidia.com id ; Tue, 30 Aug 2016 12:10:49 -0700 Received: from HQMAIL101.nvidia.com ([172.20.187.10]) by hqnvupgp07.nvidia.com (PGP Universal service); Tue, 30 Aug 2016 12:07:12 -0700 X-PGP-Universal: processed; by hqnvupgp07.nvidia.com on Tue, 30 Aug 2016 12:07:12 -0700 Received: from UKMAIL102.nvidia.com (10.26.138.15) by HQMAIL101.nvidia.com (172.20.187.10) with Microsoft SMTP Server (TLS) id 15.0.1210.3; Tue, 30 Aug 2016 19:11:36 +0000 Received: from HQMAIL103.nvidia.com (172.20.187.11) by UKMAIL102.nvidia.com (10.26.138.15) with Microsoft SMTP Server (TLS) id 15.0.1210.3; Tue, 30 Aug 2016 19:11:33 +0000 Received: from shardar-build-machine.nvidia.com (172.20.13.39) by HQMAIL103.nvidia.com (172.20.187.11) with Microsoft SMTP Server (TLS) id 15.0.1210.3 via Frontend Transport; Tue, 30 Aug 2016 19:11:30 +0000 From: Shardar Shariff Md To: , , , , , , , , Subject: [PATCH v10 2/4] i2c: tegra: add separate function for config_load programing Date: Wed, 31 Aug 2016 00:41:17 +0530 Message-ID: <1472584279-19924-2-git-send-email-smohammed@nvidia.com> X-Mailer: git-send-email 1.8.1.5 In-Reply-To: <1472584279-19924-1-git-send-email-smohammed@nvidia.com> References: <1472584279-19924-1-git-send-email-smohammed@nvidia.com> MIME-Version: 1.0 Sender: linux-tegra-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: linux-tegra@vger.kernel.org Define separate function for configuration load register handling to make it use by different functions later. Signed-off-by: Shardar Shariff Md --- Changes in v2: - Remove unnecessary paranthesis and align to 80 characters per line Changes in v3: - Add separate function for config load handling Changes in v4: - Move timeout calculation to separate patch Changes in v9: - Rebase with the changes to earlier patch1 Changes in v10: - Rebase on top of [PATCH V2 0/9] Some Tegra I2C Updates --- --- drivers/i2c/busses/i2c-tegra.c | 42 ++++++++++++++++++++++++++---------------- 1 file changed, 26 insertions(+), 16 deletions(-) diff --git a/drivers/i2c/busses/i2c-tegra.c b/drivers/i2c/busses/i2c-tegra.c index 5eb37ab..5e94056 100644 --- a/drivers/i2c/busses/i2c-tegra.c +++ b/drivers/i2c/busses/i2c-tegra.c @@ -446,6 +446,29 @@ static int tegra_i2c_runtime_suspend(struct device *dev) return pinctrl_pm_select_idle_state(i2c_dev->dev); } +static int tegra_i2c_wait_for_config_load(struct tegra_i2c_dev *i2c_dev) +{ + unsigned long reg_offset; + void __iomem *addr; + u32 val; + int err; + + if (i2c_dev->hw->has_config_load_reg) { + reg_offset = tegra_i2c_reg_addr(i2c_dev, I2C_CONFIG_LOAD); + addr = i2c_dev->base + reg_offset; + i2c_writel(i2c_dev, I2C_MSTR_CONFIG_LOAD, I2C_CONFIG_LOAD); + err = readl_poll_timeout(addr, val, val == 0, 1000, + I2C_CONFIG_LOAD_TIMEOUT); + if (err) { + dev_warn(i2c_dev->dev, + "timeout waiting for config load\n"); + return err; + } + } + + return 0; +} + static int tegra_i2c_init(struct tegra_i2c_dev *i2c_dev) { u32 val; @@ -498,22 +521,9 @@ static int tegra_i2c_init(struct tegra_i2c_dev *i2c_dev) if (i2c_dev->is_multimaster_mode && i2c_dev->hw->has_slcg_override_reg) i2c_writel(i2c_dev, I2C_MST_CORE_CLKEN_OVR, I2C_CLKEN_OVERRIDE); - if (i2c_dev->hw->has_config_load_reg) { - unsigned long reg_offset; - void __iomem *addr; - u32 val; - - reg_offset = tegra_i2c_reg_addr(i2c_dev, I2C_CONFIG_LOAD); - addr = i2c_dev->base + reg_offset; - i2c_writel(i2c_dev, I2C_MSTR_CONFIG_LOAD, I2C_CONFIG_LOAD); - err = readl_poll_timeout(addr, val, val == 0, 1000, - I2C_CONFIG_LOAD_TIMEOUT); - if (err) { - dev_warn(i2c_dev->dev, - "timeout waiting for config load\n"); - goto err; - } - } + err = tegra_i2c_wait_for_config_load(i2c_dev); + if (err) + goto err; if (i2c_dev->irq_disabled) { i2c_dev->irq_disabled = 0;