From patchwork Wed Aug 10 05:23:28 2016 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Vince Hsu X-Patchwork-Id: 657801 Return-Path: X-Original-To: incoming@patchwork.ozlabs.org Delivered-To: patchwork-incoming@bilbo.ozlabs.org Received: from vger.kernel.org (vger.kernel.org [209.132.180.67]) by ozlabs.org (Postfix) with ESMTP id 3s8g6H2PFgz9rxl for ; Thu, 11 Aug 2016 04:44:07 +1000 (AEST) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S936532AbcHJSny (ORCPT ); Wed, 10 Aug 2016 14:43:54 -0400 Received: from hqemgate16.nvidia.com ([216.228.121.65]:17766 "EHLO hqemgate16.nvidia.com" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S936512AbcHJSnw (ORCPT ); Wed, 10 Aug 2016 14:43:52 -0400 Received: from hqnvupgp07.nvidia.com (Not Verified[216.228.121.13]) by hqemgate16.nvidia.com id ; Tue, 09 Aug 2016 22:23:15 -0700 Received: from HQMAIL108.nvidia.com ([172.18.146.13]) by hqnvupgp07.nvidia.com (PGP Universal service); Tue, 09 Aug 2016 22:19:54 -0700 X-PGP-Universal: processed; by hqnvupgp07.nvidia.com on Tue, 09 Aug 2016 22:19:54 -0700 Received: from HQMAIL108.nvidia.com (172.18.146.13) by HQMAIL108.nvidia.com (172.18.146.13) with Microsoft SMTP Server (TLS) id 15.0.1210.3; Wed, 10 Aug 2016 05:23:12 +0000 Received: from hqnvemgw01.nvidia.com (172.20.150.20) by HQMAIL108.nvidia.com (172.18.146.13) with Microsoft SMTP Server id 15.0.1210.3 via Frontend Transport; Wed, 10 Aug 2016 05:23:12 +0000 Received: from krait.nvidia.com (Not Verified[10.19.41.246]) by hqnvemgw01.nvidia.com with Trustwave SEG (v7, 5, 5, 8150) id ; Tue, 09 Aug 2016 22:23:12 -0700 From: Vince Hsu To: , , , CC: , Vince Hsu Subject: [PATCH] soc/tegra: pmc: Fix incorrect DPD request Date: Wed, 10 Aug 2016 13:23:28 +0800 Message-ID: <1470806608-23231-1-git-send-email-vinceh@nvidia.com> X-Mailer: git-send-email 2.7.4 X-NVConfidentiality: public MIME-Version: 1.0 Sender: linux-tegra-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: linux-tegra@vger.kernel.org Reading the DPD_REQ & DPD2_REQ registers returns the previous requests. If we sets the current request bit with the returned value, then other pads will be turned on or off unexpectedly. Signed-off-by: Vince Hsu --- Hi, I found this issue when debugging one HDMI issue which only happened after LP0 on Tegra124 chromebook. I did not test this patch on any upstream platforms due to lack of setup, but it did pass Nvidia internal EMIT verification. Thanks, Vince drivers/soc/tegra/pmc.c | 6 ++---- 1 file changed, 2 insertions(+), 4 deletions(-) diff --git a/drivers/soc/tegra/pmc.c b/drivers/soc/tegra/pmc.c index 71c834f3847e..43c01a85334c 100644 --- a/drivers/soc/tegra/pmc.c +++ b/drivers/soc/tegra/pmc.c @@ -979,8 +979,7 @@ int tegra_io_rail_power_on(unsigned int id) mask = 1 << bit; - value = tegra_pmc_readl(request); - value |= mask; + value = mask; value &= ~IO_DPD_REQ_CODE_MASK; value |= IO_DPD_REQ_CODE_OFF; tegra_pmc_writel(value, request); @@ -1016,8 +1015,7 @@ int tegra_io_rail_power_off(unsigned int id) mask = 1 << bit; - value = tegra_pmc_readl(request); - value |= mask; + value = mask; value &= ~IO_DPD_REQ_CODE_MASK; value |= IO_DPD_REQ_CODE_ON; tegra_pmc_writel(value, request);