From patchwork Tue Aug 2 10:34:26 2016 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Jon Hunter X-Patchwork-Id: 654638 X-Patchwork-Delegate: treding@nvidia.com Return-Path: X-Original-To: incoming@patchwork.ozlabs.org Delivered-To: patchwork-incoming@bilbo.ozlabs.org Received: from vger.kernel.org (vger.kernel.org [209.132.180.67]) by ozlabs.org (Postfix) with ESMTP id 3s3Xds25hPz9t3Q for ; Tue, 2 Aug 2016 20:35:13 +1000 (AEST) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1753017AbcHBKfK (ORCPT ); Tue, 2 Aug 2016 06:35:10 -0400 Received: from hqemgate15.nvidia.com ([216.228.121.64]:1231 "EHLO hqemgate15.nvidia.com" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1752000AbcHBKfH (ORCPT ); Tue, 2 Aug 2016 06:35:07 -0400 Received: from hqnvupgp07.nvidia.com (Not Verified[216.228.121.13]) by hqemgate15.nvidia.com id ; Tue, 02 Aug 2016 03:34:40 -0700 Received: from HQMAIL101.nvidia.com ([172.20.187.10]) by hqnvupgp07.nvidia.com (PGP Universal service); Tue, 02 Aug 2016 03:31:46 -0700 X-PGP-Universal: processed; by hqnvupgp07.nvidia.com on Tue, 02 Aug 2016 03:31:46 -0700 Received: from HQMAIL103.nvidia.com (172.20.187.11) by HQMAIL101.nvidia.com (172.20.187.10) with Microsoft SMTP Server (TLS) id 15.0.1210.3; Tue, 2 Aug 2016 10:34:39 +0000 Received: from hqnvemgw02.nvidia.com (172.16.227.111) by HQMAIL103.nvidia.com (172.20.187.11) with Microsoft SMTP Server id 15.0.1210.3 via Frontend Transport; Tue, 2 Aug 2016 10:34:39 +0000 Received: from jonathanh-lm.nvidia.com (Not Verified[10.26.11.39]) by hqnvemgw02.nvidia.com with Trustwave SEG (v7, 5, 5, 8150) id ; Tue, 02 Aug 2016 03:34:38 -0700 From: Jon Hunter To: Stephen Warren , Thierry Reding , Alexandre Courbot CC: , , Jon Hunter Subject: [PATCH 1/4] drm/tegra: dc: Don't disable display power partition Date: Tue, 2 Aug 2016 11:34:26 +0100 Message-ID: <1470134069-12178-2-git-send-email-jonathanh@nvidia.com> X-Mailer: git-send-email 2.1.4 In-Reply-To: <1470134069-12178-1-git-send-email-jonathanh@nvidia.com> References: <1470134069-12178-1-git-send-email-jonathanh@nvidia.com> X-NVConfidentiality: public MIME-Version: 1.0 Sender: linux-tegra-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: linux-tegra@vger.kernel.org Commit 33a8eb8d40ee ("drm/tegra: dc: Implement runtime PM") disables the display power partition when probing and this causes the Tegra114 Dalmore to hang during boot. The hang occurs when accessing the MIPI calibration registers (which are accessed during the configuration of the DSI interface). Ideally the MIPI driver should manage the power partition itself to ensure it is on when needed. The problem is that the legacy PMC APIs used for managing the power partitions do not support reference counting and so this cannot be easily done currently. Long-term we will migrate devices to use generic PM domains and such scenarios will be easy to support. For now fix this by removing the code to turn off the display power partition when probing the DC and always keep the DC on so that the power partition is not turned off. This is consistent with how the power partition was managed prior to this commit. Please note that for earlier devices such as Tegra114 the MIPI calibration logic is part of the display power partition, where as for newer devices, such as Tegra124/210 it is part of the SOR power partition. Hence, in the long-term is makes more sense to handle such power partitions via the generic PM domain framework. Fixes: 33a8eb8d40ee ("drm/tegra: dc: Implement runtime PM") Signed-off-by: Jon Hunter --- Please note that the hang is only seen on Tegra114 with v4.8 if the patch "ARM: tegra: Correct polarity for Tegra114 PMIC interrupt" (2nd patch in series) is applied without this patch. Without the fix for the PMIC interrupt polarity the Palmas PMIC probe fails and the display probe also fails because the regulators are not found. drivers/gpu/drm/tegra/dc.c | 21 ++++++++++++++------- 1 file changed, 14 insertions(+), 7 deletions(-) diff --git a/drivers/gpu/drm/tegra/dc.c b/drivers/gpu/drm/tegra/dc.c index 8495bd01b544..17bd80a745d6 100644 --- a/drivers/gpu/drm/tegra/dc.c +++ b/drivers/gpu/drm/tegra/dc.c @@ -1217,8 +1217,6 @@ static void tegra_crtc_disable(struct drm_crtc *crtc) tegra_dc_stats_reset(&dc->stats); drm_crtc_vblank_off(crtc); - - pm_runtime_put_sync(dc->dev); } static void tegra_crtc_enable(struct drm_crtc *crtc) @@ -1228,8 +1226,6 @@ static void tegra_crtc_enable(struct drm_crtc *crtc) struct tegra_dc *dc = to_tegra_dc(crtc); u32 value; - pm_runtime_get_sync(dc->dev); - /* initialize display controller */ if (dc->syncpt) { u32 syncpt = host1x_syncpt_id(dc->syncpt); @@ -1997,8 +1993,6 @@ static int tegra_dc_probe(struct platform_device *pdev) dc->powergate = TEGRA_POWERGATE_DIS; else dc->powergate = TEGRA_POWERGATE_DISB; - - tegra_powergate_power_off(dc->powergate); } regs = platform_get_resource(pdev, IORESOURCE_MEM, 0); @@ -2020,6 +2014,11 @@ static int tegra_dc_probe(struct platform_device *pdev) platform_set_drvdata(pdev, dc); pm_runtime_enable(&pdev->dev); + err = pm_runtime_get_sync(&pdev->dev); + if (err < 0) { + dev_err(&pdev->dev, "failed to enable device: %d\n", err); + goto rpm_disable; + } INIT_LIST_HEAD(&dc->client.list); dc->client.ops = &dc_client_ops; @@ -2029,10 +2028,17 @@ static int tegra_dc_probe(struct platform_device *pdev) if (err < 0) { dev_err(&pdev->dev, "failed to register host1x client: %d\n", err); - return err; + goto rpm_put; } return 0; + +rpm_put: + pm_runtime_put_sync(&pdev->dev); +rpm_disable: + pm_runtime_disable(&pdev->dev); + + return err; } static int tegra_dc_remove(struct platform_device *pdev) @@ -2053,6 +2059,7 @@ static int tegra_dc_remove(struct platform_device *pdev) return err; } + pm_runtime_put_sync(&pdev->dev); pm_runtime_disable(&pdev->dev); return 0;