From patchwork Fri Jun 17 13:06:13 2016 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Laxman Dewangan X-Patchwork-Id: 637019 X-Patchwork-Delegate: treding@nvidia.com Return-Path: X-Original-To: incoming@patchwork.ozlabs.org Delivered-To: patchwork-incoming@bilbo.ozlabs.org Received: from vger.kernel.org (vger.kernel.org [209.132.180.67]) by ozlabs.org (Postfix) with ESMTP id 3rWLVP0GC3z9t2F for ; Fri, 17 Jun 2016 23:21:01 +1000 (AEST) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S932315AbcFQNT5 (ORCPT ); Fri, 17 Jun 2016 09:19:57 -0400 Received: from nat-hk.nvidia.com ([203.18.50.4]:16276 "EHLO hkmmgate101.nvidia.com" rhost-flags-OK-OK-OK-FAIL) by vger.kernel.org with ESMTP id S1753405AbcFQNTz (ORCPT ); Fri, 17 Jun 2016 09:19:55 -0400 Received: from hkpgpgate102.nvidia.com (Not Verified[10.18.92.9]) by hkmmgate101.nvidia.com id ; Fri, 17 Jun 2016 21:19:56 +0800 Received: from HKMAIL102.nvidia.com ([10.18.67.137]) by hkpgpgate102.nvidia.com (PGP Universal service); Fri, 17 Jun 2016 06:19:52 -0700 X-PGP-Universal: processed; by hkpgpgate102.nvidia.com on Fri, 17 Jun 2016 06:19:52 -0700 Received: from DRBGMAIL101.nvidia.com (10.18.16.20) by HKMAIL102.nvidia.com (10.18.16.11) with Microsoft SMTP Server (TLS) id 15.0.1130.7; Fri, 17 Jun 2016 13:19:50 +0000 Received: from HQMAIL103.nvidia.com (172.20.187.11) by DRBGMAIL101.nvidia.com (10.18.16.20) with Microsoft SMTP Server (TLS) id 15.0.1130.7; Fri, 17 Jun 2016 13:19:49 +0000 Received: from ldewanganubuntu-System-Product-Name.nvidia.com (172.20.13.39) by HQMAIL103.nvidia.com (172.20.187.11) with Microsoft SMTP Server id 15.0.1130.7 via Frontend Transport; Fri, 17 Jun 2016 13:19:45 +0000 From: Laxman Dewangan To: , , , , , , , CC: Laxman Dewangan Subject: [PATCH V8 2/3] soc/tegra: pmc: Correct type of variable for tegra_pmc_readl() Date: Fri, 17 Jun 2016 18:36:13 +0530 Message-ID: <1466168774-13707-3-git-send-email-ldewangan@nvidia.com> X-Mailer: git-send-email 2.1.4 In-Reply-To: <1466168774-13707-1-git-send-email-ldewangan@nvidia.com> References: <1466168774-13707-1-git-send-email-ldewangan@nvidia.com> MIME-Version: 1.0 Sender: linux-tegra-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: linux-tegra@vger.kernel.org The function tegra_pmc_readl() returns the u32 type data and hence change the data type of variable where this data is stored to u32 type. Signed-off-by: Laxman Dewangan Reviewed-by: Jon Hunter --- Changes from V1: -This is new in series as per discussion on V1 series to use u32 for tegra_pmc_readl. Changes from V2: - Make unsigned long to u32 for some missed variable from V1. Changes from V3: - Revert back the value to ulong where time calcualtion is done. Changes from V4: - Collected RB from Jon. Changes from V5/V6: - None --- drivers/soc/tegra/pmc.c | 16 +++++++++------- 1 file changed, 9 insertions(+), 7 deletions(-) diff --git a/drivers/soc/tegra/pmc.c b/drivers/soc/tegra/pmc.c index 6b61ec6..288dcb7 100644 --- a/drivers/soc/tegra/pmc.c +++ b/drivers/soc/tegra/pmc.c @@ -885,10 +885,10 @@ static int tegra_io_rail_prepare(unsigned int id, unsigned long *request, return 0; } -static int tegra_io_rail_poll(unsigned long offset, unsigned long mask, - unsigned long val, unsigned long timeout) +static int tegra_io_rail_poll(unsigned long offset, u32 mask, + u32 val, unsigned long timeout) { - unsigned long value; + u32 value; timeout = jiffies + msecs_to_jiffies(timeout); @@ -910,8 +910,9 @@ static void tegra_io_rail_unprepare(void) int tegra_io_rail_power_on(unsigned int id) { - unsigned long request, status, value; - unsigned int bit, mask; + unsigned long request, status; + unsigned int bit; + u32 value, mask; int err; mutex_lock(&pmc->powergates_lock); @@ -945,8 +946,9 @@ EXPORT_SYMBOL(tegra_io_rail_power_on); int tegra_io_rail_power_off(unsigned int id) { - unsigned long request, status, value; - unsigned int bit, mask; + unsigned long request, status; + unsigned int bit; + u32 value, mask; int err; mutex_lock(&pmc->powergates_lock);