| Message ID | 1452799478-14791-6-git-send-email-rklein@nvidia.com |
|---|---|
| State | Accepted, archived |
| Headers | show |
On Thu, Jan 14, 2016 at 02:24:34PM -0500, Rhyland Klein wrote: > From: Andrew Bresticker <abrestic@chromium.org> > > Since the ->enable() callback is called with a spinlock held, we cannot > call potentially blocking functions such as clk_get_rate() or > clk_get_parent(), so use the unlocked versions instead. > > Signed-off-by: Andrew Bresticker <abrestic@chromium.org> > [rklein: Adapted from ChromeOS patch, removing pllu_enable cleanup as > it isn't present upstream] > Signed-off-by: Rhyland Klein <rklein@nvidia.com> > --- > drivers/clk/tegra/clk-pll.c | 6 +++--- > 1 file changed, 3 insertions(+), 3 deletions(-) Applied, thanks. Thierry
On Thu, Jan 14, 2016 at 02:24:34PM -0500, Rhyland Klein wrote: > From: Andrew Bresticker <abrestic@chromium.org> > > Since the ->enable() callback is called with a spinlock held, we cannot > call potentially blocking functions such as clk_get_rate() or > clk_get_parent(), so use the unlocked versions instead. > > Signed-off-by: Andrew Bresticker <abrestic@chromium.org> > [rklein: Adapted from ChromeOS patch, removing pllu_enable cleanup as > it isn't present upstream] > Signed-off-by: Rhyland Klein <rklein@nvidia.com> > --- > drivers/clk/tegra/clk-pll.c | 6 +++--- > 1 file changed, 3 insertions(+), 3 deletions(-) Applied, thanks. Thierry
diff --git a/drivers/clk/tegra/clk-pll.c b/drivers/clk/tegra/clk-pll.c index a534bfab30b3..65156486889a 100644 --- a/drivers/clk/tegra/clk-pll.c +++ b/drivers/clk/tegra/clk-pll.c @@ -880,7 +880,7 @@ static int clk_plle_training(struct tegra_clk_pll *pll) static int clk_plle_enable(struct clk_hw *hw) { struct tegra_clk_pll *pll = to_clk_pll(hw); - unsigned long input_rate = clk_get_rate(clk_get_parent(hw->clk)); + unsigned long input_rate = clk_hw_get_rate(clk_hw_get_parent(hw)); struct tegra_clk_pll_freq_table sel; u32 val; int err; @@ -1378,7 +1378,7 @@ static int clk_plle_tegra114_enable(struct clk_hw *hw) u32 val; int ret; unsigned long flags = 0; - unsigned long input_rate = clk_get_rate(clk_get_parent(hw->clk)); + unsigned long input_rate = clk_hw_get_rate(clk_hw_get_parent(hw)); if (_get_table_rate(hw, &sel, pll->params->fixed_rate, input_rate)) return -EINVAL; @@ -2014,7 +2014,7 @@ static int clk_plle_tegra210_enable(struct clk_hw *hw) u32 val; int ret; unsigned long flags = 0; - unsigned long input_rate = clk_get_rate(clk_get_parent(hw->clk)); + unsigned long input_rate = clk_hw_get_rate(clk_hw_get_parent(hw)); if (_get_table_rate(hw, &sel, pll->params->fixed_rate, input_rate)) return -EINVAL;