diff mbox

[v3,03/13] soc/tegra: Add ram code reader helper

Message ID 1414599796-30597-4-git-send-email-tomeu.vizoso@collabora.com
State Superseded, archived
Headers show

Commit Message

Tomeu Vizoso Oct. 29, 2014, 4:22 p.m. UTC 
From: Mikko Perttunen <mperttunen@nvidia.com>

Needed for the EMC and MC drivers to know what timings from the DT to use.

Signed-off-by: Mikko Perttunen <mperttunen@nvidia.com>
Signed-off-by: Tomeu Vizoso <tomeu.vizoso@collabora.com>
---
 drivers/soc/tegra/fuse/tegra-apbmisc.c | 19 +++++++++++++++++++
 include/soc/tegra/fuse.h               |  1 +
 2 files changed, 20 insertions(+)

Comments

Alexandre Courbot Nov. 6, 2014, 5:25 a.m. UTC | #1 
On 10/30/2014 01:22 AM, Tomeu Vizoso wrote:
> From: Mikko Perttunen <mperttunen@nvidia.com>
>
> Needed for the EMC and MC drivers to know what timings from the DT to use.
>
> Signed-off-by: Mikko Perttunen <mperttunen@nvidia.com>
> Signed-off-by: Tomeu Vizoso <tomeu.vizoso@collabora.com>
> ---
>   drivers/soc/tegra/fuse/tegra-apbmisc.c | 19 +++++++++++++++++++
>   include/soc/tegra/fuse.h               |  1 +
>   2 files changed, 20 insertions(+)
>
> diff --git a/drivers/soc/tegra/fuse/tegra-apbmisc.c b/drivers/soc/tegra/fuse/tegra-apbmisc.c
> index 3bf5aba..e580892 100644
> --- a/drivers/soc/tegra/fuse/tegra-apbmisc.c
> +++ b/drivers/soc/tegra/fuse/tegra-apbmisc.c
> @@ -28,8 +28,13 @@
>   #define APBMISC_SIZE	0x64
>   #define FUSE_SKU_INFO	0x10
>
> +#define PMC_STRAPPING_OPT_A_RAM_CODE_MASK_LONG	(0xf << 4)
> +#define PMC_STRAPPING_OPT_A_RAM_CODE_MASK_SHORT	(0x3 << 4)

Shouldn't these two shifts also use PMC_STRAPPING_OPT_A_RAM_CODE_SHIFT 
defined right after?

> +#define PMC_STRAPPING_OPT_A_RAM_CODE_SHIFT	4
> +
>   static void __iomem *apbmisc_base;
>   static void __iomem *strapping_base;
> +static bool          long_ram_code;
>
>   u32 tegra_read_chipid(void)
>   {
> @@ -54,6 +59,18 @@ u32 tegra_read_straps(void)
>   		return 0;
>   }
>
> +u32 tegra_read_ram_code(void)
> +{
> +	u32 straps = tegra_read_straps();
> +
> +	if (long_ram_code)
> +		straps &= PMC_STRAPPING_OPT_A_RAM_CODE_MASK_LONG;
> +	else
> +		straps &= PMC_STRAPPING_OPT_A_RAM_CODE_MASK_SHORT;
> +
> +	return straps >> PMC_STRAPPING_OPT_A_RAM_CODE_SHIFT;

... this is what triggered my remark above, since it seems like you want 
to return the ram_code field.

> +}
> +
>   static const struct of_device_id apbmisc_match[] __initconst = {
>   	{ .compatible = "nvidia,tegra20-apbmisc", },
>   	{},
> @@ -112,4 +129,6 @@ void __init tegra_init_apbmisc(void)
>   	strapping_base = of_iomap(np, 1);
>   	if (!strapping_base)
>   		pr_err("ioremap tegra strapping_base failed\n");
> +
> +	long_ram_code = of_property_read_bool(np, "nvidia,long-ram-code");
>   }
> diff --git a/include/soc/tegra/fuse.h b/include/soc/tegra/fuse.h
> index 8e12494..4ad6fd9 100644
> --- a/include/soc/tegra/fuse.h
> +++ b/include/soc/tegra/fuse.h
> @@ -55,6 +55,7 @@ struct tegra_sku_info {
>   };
>
>   u32 tegra_read_straps(void);
> +u32 tegra_read_ram_code(void);
>   u32 tegra_read_chipid(void);
>   int tegra_fuse_readl(unsigned long offset, u32 *value);
>
>

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Tomeu Vizoso Nov. 6, 2014, 9:07 a.m. UTC | #2 
On 6 November 2014 06:25, Alexandre Courbot <acourbot@nvidia.com> wrote:
> On 10/30/2014 01:22 AM, Tomeu Vizoso wrote:
>>
>> From: Mikko Perttunen <mperttunen@nvidia.com>
>>
>> Needed for the EMC and MC drivers to know what timings from the DT to use.
>>
>> Signed-off-by: Mikko Perttunen <mperttunen@nvidia.com>
>> Signed-off-by: Tomeu Vizoso <tomeu.vizoso@collabora.com>
>> ---
>>   drivers/soc/tegra/fuse/tegra-apbmisc.c | 19 +++++++++++++++++++
>>   include/soc/tegra/fuse.h               |  1 +
>>   2 files changed, 20 insertions(+)
>>
>> diff --git a/drivers/soc/tegra/fuse/tegra-apbmisc.c
>> b/drivers/soc/tegra/fuse/tegra-apbmisc.c
>> index 3bf5aba..e580892 100644
>> --- a/drivers/soc/tegra/fuse/tegra-apbmisc.c
>> +++ b/drivers/soc/tegra/fuse/tegra-apbmisc.c
>> @@ -28,8 +28,13 @@
>>   #define APBMISC_SIZE  0x64
>>   #define FUSE_SKU_INFO 0x10
>>
>> +#define PMC_STRAPPING_OPT_A_RAM_CODE_MASK_LONG (0xf << 4)
>> +#define PMC_STRAPPING_OPT_A_RAM_CODE_MASK_SHORT        (0x3 << 4)
>
>
> Shouldn't these two shifts also use PMC_STRAPPING_OPT_A_RAM_CODE_SHIFT
> defined right after?

Good point.

Thanks,

Tomeu

>> +#define PMC_STRAPPING_OPT_A_RAM_CODE_SHIFT     4
>> +
>>   static void __iomem *apbmisc_base;
>>   static void __iomem *strapping_base;
>> +static bool          long_ram_code;
>>
>>   u32 tegra_read_chipid(void)
>>   {
>> @@ -54,6 +59,18 @@ u32 tegra_read_straps(void)
>>                 return 0;
>>   }
>>
>> +u32 tegra_read_ram_code(void)
>> +{
>> +       u32 straps = tegra_read_straps();
>> +
>> +       if (long_ram_code)
>> +               straps &= PMC_STRAPPING_OPT_A_RAM_CODE_MASK_LONG;
>> +       else
>> +               straps &= PMC_STRAPPING_OPT_A_RAM_CODE_MASK_SHORT;
>> +
>> +       return straps >> PMC_STRAPPING_OPT_A_RAM_CODE_SHIFT;
>
>
> ... this is what triggered my remark above, since it seems like you want to
> return the ram_code field.
>
>> +}
>> +
>>   static const struct of_device_id apbmisc_match[] __initconst = {
>>         { .compatible = "nvidia,tegra20-apbmisc", },
>>         {},
>> @@ -112,4 +129,6 @@ void __init tegra_init_apbmisc(void)
>>         strapping_base = of_iomap(np, 1);
>>         if (!strapping_base)
>>                 pr_err("ioremap tegra strapping_base failed\n");
>> +
>> +       long_ram_code = of_property_read_bool(np, "nvidia,long-ram-code");
>>   }
>> diff --git a/include/soc/tegra/fuse.h b/include/soc/tegra/fuse.h
>> index 8e12494..4ad6fd9 100644
>> --- a/include/soc/tegra/fuse.h
>> +++ b/include/soc/tegra/fuse.h
>> @@ -55,6 +55,7 @@ struct tegra_sku_info {
>>   };
>>
>>   u32 tegra_read_straps(void);
>> +u32 tegra_read_ram_code(void);
>>   u32 tegra_read_chipid(void);
>>   int tegra_fuse_readl(unsigned long offset, u32 *value);
>>
>>
>
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diff mbox

Patch

diff --git a/drivers/soc/tegra/fuse/tegra-apbmisc.c b/drivers/soc/tegra/fuse/tegra-apbmisc.c
index 3bf5aba..e580892 100644
--- a/drivers/soc/tegra/fuse/tegra-apbmisc.c
+++ b/drivers/soc/tegra/fuse/tegra-apbmisc.c
@@ -28,8 +28,13 @@ 
 #define APBMISC_SIZE	0x64
 #define FUSE_SKU_INFO	0x10
 
+#define PMC_STRAPPING_OPT_A_RAM_CODE_MASK_LONG	(0xf << 4)
+#define PMC_STRAPPING_OPT_A_RAM_CODE_MASK_SHORT	(0x3 << 4)
+#define PMC_STRAPPING_OPT_A_RAM_CODE_SHIFT	4
+
 static void __iomem *apbmisc_base;
 static void __iomem *strapping_base;
+static bool          long_ram_code;
 
 u32 tegra_read_chipid(void)
 {
@@ -54,6 +59,18 @@  u32 tegra_read_straps(void)
 		return 0;
 }
 
+u32 tegra_read_ram_code(void)
+{
+	u32 straps = tegra_read_straps();
+
+	if (long_ram_code)
+		straps &= PMC_STRAPPING_OPT_A_RAM_CODE_MASK_LONG;
+	else
+		straps &= PMC_STRAPPING_OPT_A_RAM_CODE_MASK_SHORT;
+
+	return straps >> PMC_STRAPPING_OPT_A_RAM_CODE_SHIFT;
+}
+
 static const struct of_device_id apbmisc_match[] __initconst = {
 	{ .compatible = "nvidia,tegra20-apbmisc", },
 	{},
@@ -112,4 +129,6 @@  void __init tegra_init_apbmisc(void)
 	strapping_base = of_iomap(np, 1);
 	if (!strapping_base)
 		pr_err("ioremap tegra strapping_base failed\n");
+
+	long_ram_code = of_property_read_bool(np, "nvidia,long-ram-code");
 }
diff --git a/include/soc/tegra/fuse.h b/include/soc/tegra/fuse.h
index 8e12494..4ad6fd9 100644
--- a/include/soc/tegra/fuse.h
+++ b/include/soc/tegra/fuse.h
@@ -55,6 +55,7 @@  struct tegra_sku_info {
 };
 
 u32 tegra_read_straps(void);
+u32 tegra_read_ram_code(void);
 u32 tegra_read_chipid(void);
 int tegra_fuse_readl(unsigned long offset, u32 *value);