From patchwork Mon Apr 21 06:02:19 2014 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Alexandre Courbot X-Patchwork-Id: 340595 Return-Path: X-Original-To: incoming@patchwork.ozlabs.org Delivered-To: patchwork-incoming@bilbo.ozlabs.org Received: from vger.kernel.org (vger.kernel.org [209.132.180.67]) by ozlabs.org (Postfix) with ESMTP id E9FB8140106 for ; Mon, 21 Apr 2014 16:04:18 +1000 (EST) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1751640AbaDUGEN (ORCPT ); Mon, 21 Apr 2014 02:04:13 -0400 Received: from hqemgate15.nvidia.com ([216.228.121.64]:3882 "EHLO hqemgate15.nvidia.com" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1751507AbaDUGEH (ORCPT ); Mon, 21 Apr 2014 02:04:07 -0400 Received: from hqnvupgp08.nvidia.com (Not Verified[216.228.121.13]) by hqemgate15.nvidia.com id ; Sun, 20 Apr 2014 23:02:55 -0700 Received: from hqemhub03.nvidia.com ([172.20.12.94]) by hqnvupgp08.nvidia.com (PGP Universal service); Sun, 20 Apr 2014 22:58:42 -0700 X-PGP-Universal: processed; by hqnvupgp08.nvidia.com on Sun, 20 Apr 2014 22:58:42 -0700 Received: from percival.nvidia.com (172.20.144.16) by hqemhub03.nvidia.com (172.20.150.15) with Microsoft SMTP Server (TLS) id 8.3.327.1; Sun, 20 Apr 2014 23:03:34 -0700 From: Alexandre Courbot To: Ben Skeggs CC: Thierry Reding , , , , , , Alexandre Courbot Subject: [PATCH v2 07/10] drm/nouveau/graph: pad firmware code at load time Date: Mon, 21 Apr 2014 15:02:19 +0900 Message-ID: <1398060142-7937-8-git-send-email-acourbot@nvidia.com> X-Mailer: git-send-email 1.9.2 In-Reply-To: <1398060142-7937-1-git-send-email-acourbot@nvidia.com> References: <1398060142-7937-1-git-send-email-acourbot@nvidia.com> X-NVConfidentiality: public MIME-Version: 1.0 Sender: linux-tegra-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: linux-tegra@vger.kernel.org Pad the microcode to a multiple of 0x40 bytes, otherwise firmware will fail to run from non-prepadded firmware files. Signed-off-by: Alexandre Courbot Reviewed-by: Thierry Reding --- drivers/gpu/drm/nouveau/core/engine/graph/nvc0.c | 4 ++++ 1 file changed, 4 insertions(+) diff --git a/drivers/gpu/drm/nouveau/core/engine/graph/nvc0.c b/drivers/gpu/drm/nouveau/core/engine/graph/nvc0.c index e5b75f189988..013475c62986 100644 --- a/drivers/gpu/drm/nouveau/core/engine/graph/nvc0.c +++ b/drivers/gpu/drm/nouveau/core/engine/graph/nvc0.c @@ -894,6 +894,10 @@ nvc0_graph_init_fw(struct nvc0_graph_priv *priv, u32 fuc_base, nv_wr32(priv, fuc_base + 0x0188, i >> 6); nv_wr32(priv, fuc_base + 0x0184, code->data[i]); } + + /* code must be padded to 0x40 bytes */ + for (; i & 0x3f; i++) + nv_wr32(priv, fuc_base + 0x0184, 0); } static void