From patchwork Thu Dec 19 16:06:18 2013 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Thierry Reding X-Patchwork-Id: 303609 Return-Path: X-Original-To: incoming@patchwork.ozlabs.org Delivered-To: patchwork-incoming@bilbo.ozlabs.org Received: from vger.kernel.org (vger.kernel.org [209.132.180.67]) by ozlabs.org (Postfix) with ESMTP id B09562C0078 for ; Fri, 20 Dec 2013 03:08:13 +1100 (EST) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S932158Ab3LSQIF (ORCPT ); Thu, 19 Dec 2013 11:08:05 -0500 Received: from mail-bk0-f52.google.com ([209.85.214.52]:34405 "EHLO mail-bk0-f52.google.com" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S932152Ab3LSQIE (ORCPT ); Thu, 19 Dec 2013 11:08:04 -0500 Received: by mail-bk0-f52.google.com with SMTP id u14so790843bkz.11 for ; Thu, 19 Dec 2013 08:08:02 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=gmail.com; s=20120113; h=from:to:cc:subject:date:message-id:in-reply-to:references; bh=BwV9Nx5nnQ/Ec5Mcez2fjkNsdgV/RoZlRIYCb2omcQI=; b=F9JOqaKuMKln03gZL2mZiXzcqRKtCg3PsvvJlOGh173pQ4Gk7XX1MsnaxlP2r5CrXG I0M8nsOERU1jOPqPqT8Ga2vZldjKw3Uy17NhrAyeV3w7IjLjeI+A1zjhJ+RbqpCiPdIm iEi2FeGHIsJxh++A0j/Weyw9dzYKvhnPD4V0pRrzN2hLZWRvVzsooVNhQ0qsUUeQyHRW RE3KIM6QJXEyIDEdkDiknJhlFCAnKwpu/yFRu9SQuptCEq9A5L3m5dcV/sXZK12tEL48 TNedOioxtrBpbitb7/ddMaebJFNNpCFrGubvKUQsYeKli0KVdY2enDGvKsJ0sbbFhvWo D1iA== X-Received: by 10.204.100.199 with SMTP id z7mr132393bkn.62.1387469282722; Thu, 19 Dec 2013 08:08:02 -0800 (PST) Received: from localhost (port-10467.pppoe.wtnet.de. [84.46.41.12]) by mx.google.com with ESMTPSA id dg4sm3945863bkc.10.2013.12.19.08.08.01 for (version=TLSv1.2 cipher=ECDHE-RSA-AES128-GCM-SHA256 bits=128/128); Thu, 19 Dec 2013 08:08:01 -0800 (PST) From: Thierry Reding To: Stephen Warren Cc: linux-tegra@vger.kernel.org, linux-arm-kernel@lists.infradead.org Subject: [PATCH 06/10] ARM: tegra: Add SPI controller nodes for Tegra124 Date: Thu, 19 Dec 2013 17:06:18 +0100 Message-Id: <1387469182-14398-7-git-send-email-treding@nvidia.com> X-Mailer: git-send-email 1.8.4.2 In-Reply-To: <1387469182-14398-1-git-send-email-treding@nvidia.com> References: <1387469182-14398-1-git-send-email-treding@nvidia.com> Sender: linux-tegra-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: linux-tegra@vger.kernel.org The SPI controllers on Tegra124 are compatible with those found on the Tegra114 SoC. Signed-off-by: Thierry Reding --- arch/arm/boot/dts/tegra124.dtsi | 90 +++++++++++++++++++++++++++++++++++++++++ 1 file changed, 90 insertions(+) diff --git a/arch/arm/boot/dts/tegra124.dtsi b/arch/arm/boot/dts/tegra124.dtsi index 39d77aa936f9..cf4558257e8c 100644 --- a/arch/arm/boot/dts/tegra124.dtsi +++ b/arch/arm/boot/dts/tegra124.dtsi @@ -430,6 +430,96 @@ status = "disabled"; }; + spi@7000d400 { + compatible = "nvidia,tegra124-spi", "nvidia,tegra114-spi"; + reg = <0x7000d400 0x200>; + interrupts = ; + #address-cells = <1>; + #size-cells = <0>; + clocks = <&tegra_car TEGRA124_CLK_SBC1>; + clock-names = "spi"; + resets = <&tegra_car 41>; + reset-names = "spi"; + dmas = <&apbdma 15>, <&apbdma 15>; + dma-names = "rx", "tx"; + status = "disabled"; + }; + + spi@7000d600 { + compatible = "nvidia,tegra124-spi", "nvidia,tegra114-spi"; + reg = <0x7000d600 0x200>; + interrupts = ; + #address-cells = <1>; + #size-cells = <0>; + clocks = <&tegra_car TEGRA124_CLK_SBC2>; + clock-names = "spi"; + resets = <&tegra_car 44>; + reset-names = "spi"; + dmas = <&apbdma 16>, <&apbdma 16>; + dma-names = "rx", "tx"; + status = "disabled"; + }; + + spi@7000d800 { + compatible = "nvidia,tegra124-spi", "nvidia,tegra114-spi"; + reg = <0x7000d800 0x200>; + interrupts = ; + #address-cells = <1>; + #size-cells = <0>; + clocks = <&tegra_car TEGRA124_CLK_SBC3>; + clock-names = "spi"; + resets = <&tegra_car 46>; + reset-names = "spi"; + dmas = <&apbdma 17>, <&apbdma 17>; + dma-names = "rx", "tx"; + status = "disabled"; + }; + + spi@7000da00 { + compatible = "nvidia,tegra124-spi", "nvidia,tegra114-spi"; + reg = <0x7000da00 0x200>; + interrupts = ; + #address-cells = <1>; + #size-cells = <0>; + clocks = <&tegra_car TEGRA124_CLK_SBC4>; + clock-names = "spi"; + resets = <&tegra_car 68>; + reset-names = "spi"; + dmas = <&apbdma 18>, <&apbdma 18>; + dma-names = "rx", "tx"; + status = "disabled"; + }; + + spi@7000dc00 { + compatible = "nvidia,tegra124-spi", "nvidia,tegra114-spi"; + reg = <0x7000dc00 0x200>; + interrupts = ; + #address-cells = <1>; + #size-cells = <0>; + clocks = <&tegra_car TEGRA124_CLK_SBC5>; + clock-names = "spi"; + resets = <&tegra_car 104>; + reset-names = "spi"; + dmas = <&apbdma 27>, <&apbdma 27>; + dma-names = "rx", "tx"; + status = "disabled"; + }; + + spi@7000de00 { + compatible = "nvidia,tegra124-spi", "nvidia,tegra114-spi"; + reg = <0x7000de00 0x200>; + interrupts = ; + #address-cells = <1>; + #size-cells = <0>; + clocks = <&tegra_car TEGRA124_CLK_SBC6>; + clock-names = "spi"; + resets = <&tegra_car 105>; + reset-names = "spi"; + dmas = <&apbdma 28>, <&apbdma 28>; + dma-names = "rx", "tx"; + status = "disabled"; + }; + rtc@7000e000 { compatible = "nvidia,tegra124-rtc", "nvidia,tegra20-rtc"; reg = <0x7000e000 0x100>;