| Message ID | 1387331565-3994-1-git-send-email-ebrower@nvidia.com |
|---|---|
| State | Superseded, archived |
| Headers | show |
On 12/17/2013 06:52 PM, Eric Brower wrote: > Modify Tegra30 default USB2 phy_type to UTMI; this matches > power-on-reset defaults and is expected to be the common case. > > The current implementation is likely an incorrect > carry-over from Tegra20, where USB2 does default to ULPI. > diff --git a/arch/arm/boot/dts/tegra30.dtsi b/arch/arm/boot/dts/tegra30.dtsi > phy2: usb-phy@7d004000 { > compatible = "nvidia,tegra30-usb-phy"; > - reg = <0x7d004000 0x4000>; > - phy_type = "ulpi"; > + reg = <0x7d004000 0x4000 0x7d004000 0x4000>; Are you sure the second entry in the reg property is correct here? In Tegra20, the UTMI pad registers are in the USB1 (USBD) register space for both USB controllers, and I would guess the same applies for all 3 controllers on Tegra30, since both USB1 and USB3 on Tegra30 already point this reg entry at USBD's reg space, plus you've listed USBD as the clock entry for utmi-pads, rather than USB2, which would be consistent with the reg value. Still, this patch does seem to work for me... -- To unsubscribe from this list: send the line "unsubscribe linux-tegra" in the body of a message to majordomo@vger.kernel.org More majordomo info at http://vger.kernel.org/majordomo-info.html
On 12/18/2013 01:15 PM, Stephen Warren wrote: > On 12/17/2013 06:52 PM, Eric Brower wrote: >> Modify Tegra30 default USB2 phy_type to UTMI; this matches >> power-on-reset defaults and is expected to be the common case. >> >> The current implementation is likely an incorrect >> carry-over from Tegra20, where USB2 does default to ULPI. > >> diff --git a/arch/arm/boot/dts/tegra30.dtsi b/arch/arm/boot/dts/tegra30.dtsi > >> phy2: usb-phy@7d004000 { >> compatible = "nvidia,tegra30-usb-phy"; >> - reg = <0x7d004000 0x4000>; >> - phy_type = "ulpi"; >> + reg = <0x7d004000 0x4000 0x7d004000 0x4000>; > > Are you sure the second entry in the reg property is correct here? In > Tegra20, the UTMI pad registers are in the USB1 (USBD) register space > for both USB controllers, and I would guess the same applies for all 3 > controllers on Tegra30, since both USB1 and USB3 on Tegra30 already > point this reg entry at USBD's reg space, plus you've listed USBD as the > clock entry for utmi-pads, rather than USB2, which would be consistent > with the reg value. > > Still, this patch does seem to work for me... > The second entry in the reg property is indeed incorrect-- I'll send a new version of the series. Though each controller has UTMIP BIAS pad registers, bias pad settings must be configured via USB1 only; the USB2 and USB3 BIAS pad registers are a no-connect-- this explains why it works as-is (USB1 configures bias pad settings), but is not correct for the dtsi. Thanks for the catch! Eric -- To unsubscribe from this list: send the line "unsubscribe linux-tegra" in the body of a message to majordomo@vger.kernel.org More majordomo info at http://vger.kernel.org/majordomo-info.html
diff --git a/arch/arm/boot/dts/tegra30.dtsi b/arch/arm/boot/dts/tegra30.dtsi index 2bd55cf..bedd379 100644 --- a/arch/arm/boot/dts/tegra30.dtsi +++ b/arch/arm/boot/dts/tegra30.dtsi @@ -669,7 +669,7 @@ compatible = "nvidia,tegra30-ehci", "usb-ehci"; reg = <0x7d004000 0x4000>; interrupts = <GIC_SPI 21 IRQ_TYPE_LEVEL_HIGH>; - phy_type = "ulpi"; + phy_type = "utmi"; clocks = <&tegra_car TEGRA30_CLK_USB2>; nvidia,phy = <&phy2>; status = "disabled"; @@ -677,12 +677,23 @@ phy2: usb-phy@7d004000 { compatible = "nvidia,tegra30-usb-phy"; - reg = <0x7d004000 0x4000>; - phy_type = "ulpi"; + reg = <0x7d004000 0x4000 0x7d004000 0x4000>; + phy_type = "utmi"; clocks = <&tegra_car TEGRA30_CLK_USB2>, <&tegra_car TEGRA30_CLK_PLL_U>, - <&tegra_car TEGRA30_CLK_CDEV2>; - clock-names = "reg", "pll_u", "ulpi-link"; + <&tegra_car TEGRA30_CLK_USBD>; + clock-names = "reg", "pll_u", "utmi-pads"; + nvidia,hssync-start-delay = <9>; + nvidia,idle-wait-delay = <17>; + nvidia,elastic-limit = <16>; + nvidia,term-range-adj = <6>; + nvidia,xcvr-setup = <51>; + nvidia.xcvr-setup-use-fuses; + nvidia,xcvr-lsfslew = <2>; + nvidia,xcvr-lsrslew = <2>; + nvidia,xcvr-hsslew = <32>; + nvidia,hssquelch-level = <2>; + nvidia,hsdiscon-level = <5>; status = "disabled"; };
Modify Tegra30 default USB2 phy_type to UTMI; this matches power-on-reset defaults and is expected to be the common case. The current implementation is likely an incorrect carry-over from Tegra20, where USB2 does default to ULPI. Signed-off-by: Eric Brower <ebrower@nvidia.com> --- No upstream Tegra30 dts files reference USB2, so this should be a safe change; anyone using an out-of-tree dts with USB2, sparsely populated from the Tegra30 dtsi, may have an issue. arch/arm/boot/dts/tegra30.dtsi | 21 ++++++++++++++++----- 1 file changed, 16 insertions(+), 5 deletions(-)