From patchwork Thu Dec 5 12:25:19 2013 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Hiroshi Doyu X-Patchwork-Id: 297115 Return-Path: X-Original-To: incoming@patchwork.ozlabs.org Delivered-To: patchwork-incoming@bilbo.ozlabs.org Received: from vger.kernel.org (vger.kernel.org [209.132.180.67]) by ozlabs.org (Postfix) with ESMTP id B14AE2C00A6 for ; Thu, 5 Dec 2013 23:25:45 +1100 (EST) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1755961Ab3LEMZp (ORCPT ); Thu, 5 Dec 2013 07:25:45 -0500 Received: from hqemgate15.nvidia.com ([216.228.121.64]:10168 "EHLO hqemgate15.nvidia.com" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1755717Ab3LEMZo (ORCPT ); Thu, 5 Dec 2013 07:25:44 -0500 Received: from hqnvupgp07.nvidia.com (Not Verified[216.228.121.13]) by hqemgate15.nvidia.com id ; Thu, 05 Dec 2013 04:25:42 -0800 Received: from hqemhub01.nvidia.com ([172.20.12.94]) by hqnvupgp07.nvidia.com (PGP Universal service); Thu, 05 Dec 2013 04:22:42 -0800 X-PGP-Universal: processed; by hqnvupgp07.nvidia.com on Thu, 05 Dec 2013 04:22:42 -0800 Received: from hqnvemgw02.nvidia.com (172.16.227.111) by hqemhub01.nvidia.com (172.20.150.30) with Microsoft SMTP Server id 8.3.327.1; Thu, 5 Dec 2013 04:25:44 -0800 Received: from thelma.nvidia.com (Not Verified[172.16.212.77]) by hqnvemgw02.nvidia.com with MailMarshal (v7,1,2,5326) id ; Thu, 05 Dec 2013 04:25:44 -0800 Received: from oreo.Nvidia.com (dhcp-10-21-26-134.nvidia.com [10.21.26.134]) by thelma.nvidia.com (8.13.8+Sun/8.8.8) with ESMTP id rB5CPXRM024671; Thu, 5 Dec 2013 04:25:43 -0800 (PST) From: Hiroshi Doyu To: , CC: , Hiroshi Doyu , Terje Bergstrom Subject: [PATCH 6/6] iommu/tegra124: smmu: adjust TLB_FLUSH_ASID bit range Date: Thu, 5 Dec 2013 14:25:19 +0200 Message-ID: <1386246319-17851-7-git-send-email-hdoyu@nvidia.com> X-Mailer: git-send-email 1.8.1.5 In-Reply-To: <1386246319-17851-1-git-send-email-hdoyu@nvidia.com> References: <1386246319-17851-1-git-send-email-hdoyu@nvidia.com> MIME-Version: 1.0 Sender: linux-tegra-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: linux-tegra@vger.kernel.org TLB_FLUSH_ASID bit range depends on the number of asids to support other number than the current 4, especially for a new Tegra124. Based on Terje's internal patch. Signed-off-by: Hiroshi Doyu Cc: Terje Bergstrom --- drivers/iommu/tegra-smmu.c | 9 ++++++--- 1 file changed, 6 insertions(+), 3 deletions(-) diff --git a/drivers/iommu/tegra-smmu.c b/drivers/iommu/tegra-smmu.c index 9b81e3a..535b14a 100644 --- a/drivers/iommu/tegra-smmu.c +++ b/drivers/iommu/tegra-smmu.c @@ -92,11 +92,14 @@ enum { #define SMMU_TLB_FLUSH_VA_MATCH_ALL 0 #define SMMU_TLB_FLUSH_VA_MATCH_SECTION 2 #define SMMU_TLB_FLUSH_VA_MATCH_GROUP 3 -#define SMMU_TLB_FLUSH_ASID_SHIFT 29 +#define SMMU_TLB_FLUSH_ASID_SHIFT_BASE 31 #define SMMU_TLB_FLUSH_ASID_MATCH_DISABLE 0 #define SMMU_TLB_FLUSH_ASID_MATCH_ENABLE 1 #define SMMU_TLB_FLUSH_ASID_MATCH_SHIFT 31 +#define SMMU_TLB_FLUSH_ASID_SHIFT(as) \ + (SMMU_TLB_FLUSH_ASID_SHIFT_BASE - __ffs((as)->smmu->num_as)) + #define SMMU_PTC_FLUSH 0x34 #define SMMU_PTC_FLUSH_TYPE_ALL 0 #define SMMU_PTC_FLUSH_TYPE_ADR 1 @@ -563,7 +566,7 @@ static void flush_ptc_and_tlb(struct smmu_device *smmu, val = tlb_flush_va | SMMU_TLB_FLUSH_ASID_MATCH__ENABLE | - (as->asid << SMMU_TLB_FLUSH_ASID_SHIFT); + (as->asid << SMMU_TLB_FLUSH_ASID_SHIFT(as)); smmu_write(smmu, val, SMMU_TLB_FLUSH); FLUSH_SMMU_REGS(smmu); } @@ -730,7 +733,7 @@ static int alloc_pdir(struct smmu_as *as) val = SMMU_TLB_FLUSH_VA_MATCH_ALL | SMMU_TLB_FLUSH_ASID_MATCH__ENABLE | - (as->asid << SMMU_TLB_FLUSH_ASID_SHIFT); + (as->asid << SMMU_TLB_FLUSH_ASID_SHIFT(as)); smmu_write(smmu, val, SMMU_TLB_FLUSH); FLUSH_SMMU_REGS(as->smmu);