From patchwork Thu Dec 5 10:57:49 2013 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Laxman Dewangan X-Patchwork-Id: 296795 X-Patchwork-Delegate: swarren@nvidia.com Return-Path: X-Original-To: incoming@patchwork.ozlabs.org Delivered-To: patchwork-incoming@bilbo.ozlabs.org Received: from vger.kernel.org (vger.kernel.org [209.132.180.67]) by ozlabs.org (Postfix) with ESMTP id 030992C0079 for ; Thu, 5 Dec 2013 22:01:30 +1100 (EST) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1755684Ab3LELBN (ORCPT ); Thu, 5 Dec 2013 06:01:13 -0500 Received: from hqemgate16.nvidia.com ([216.228.121.65]:4024 "EHLO hqemgate16.nvidia.com" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1755689Ab3LELBK (ORCPT ); Thu, 5 Dec 2013 06:01:10 -0500 Received: from hqnvupgp08.nvidia.com (Not Verified[216.228.121.13]) by hqemgate16.nvidia.com id ; Thu, 05 Dec 2013 03:01:14 -0800 Received: from hqemhub03.nvidia.com ([172.20.12.94]) by hqnvupgp08.nvidia.com (PGP Universal service); Thu, 05 Dec 2013 02:54:27 -0800 X-PGP-Universal: processed; by hqnvupgp08.nvidia.com on Thu, 05 Dec 2013 02:54:27 -0800 Received: from hqnvemgw02.nvidia.com (172.16.227.111) by HQEMHUB03.nvidia.com (172.20.150.15) with Microsoft SMTP Server id 8.3.327.1; Thu, 5 Dec 2013 03:00:53 -0800 Received: from thelma.nvidia.com (Not Verified[172.16.212.77]) by hqnvemgw02.nvidia.com with MailMarshal (v7,1,2,5326) id ; Thu, 05 Dec 2013 03:00:53 -0800 Received: from ldewangan-ubuntu.nvidia.com (dhcp-10-19-65-30.nvidia.com [10.19.65.30]) by thelma.nvidia.com (8.13.8+Sun/8.8.8) with ESMTP id rB5B0ZWp003995; Thu, 5 Dec 2013 03:00:48 -0800 (PST) From: Laxman Dewangan To: , CC: , , , , , , , , , , , Laxman Dewangan Subject: [PATCH 3/4] ARM: tegra: select PINCTRL_TEGRA124 for Tegra124 SoC Date: Thu, 5 Dec 2013 16:27:49 +0530 Message-ID: <1386241070-4350-4-git-send-email-ldewangan@nvidia.com> X-Mailer: git-send-email 1.7.1.1 In-Reply-To: <1386241070-4350-1-git-send-email-ldewangan@nvidia.com> References: <1386241070-4350-1-git-send-email-ldewangan@nvidia.com> MIME-Version: 1.0 Sender: linux-tegra-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: linux-tegra@vger.kernel.org The pincontrol driver for Tegra124 is build through config PINCTRL_TEGRA124. Select this config option whenever Tegra124 SoC is enabled. Signed-off-by: Laxman Dewangan --- arch/arm/mach-tegra/Kconfig | 1 + 1 files changed, 1 insertions(+), 0 deletions(-) diff --git a/arch/arm/mach-tegra/Kconfig b/arch/arm/mach-tegra/Kconfig index 09e740f..807e7bc 100644 --- a/arch/arm/mach-tegra/Kconfig +++ b/arch/arm/mach-tegra/Kconfig @@ -63,6 +63,7 @@ config ARCH_TEGRA_124_SOC bool "Enable support for Tegra124 family" select ARM_L1_CACHE_SHIFT_6 select HAVE_ARM_ARCH_TIMER + select PINCTRL_TEGRA124 help Support for NVIDIA Tegra T124 processor family, based on the ARM CortexA15MP CPU