From patchwork Thu Jun 6 10:47:29 2013 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Peter De Schrijver X-Patchwork-Id: 249379 Return-Path: X-Original-To: incoming@patchwork.ozlabs.org Delivered-To: patchwork-incoming@bilbo.ozlabs.org Received: from vger.kernel.org (vger.kernel.org [209.132.180.67]) by ozlabs.org (Postfix) with ESMTP id 581B02C009E for ; Thu, 6 Jun 2013 20:50:57 +1000 (EST) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S932502Ab3FFKun (ORCPT ); Thu, 6 Jun 2013 06:50:43 -0400 Received: from hqemgate04.nvidia.com ([216.228.121.35]:10120 "EHLO hqemgate04.nvidia.com" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S932390Ab3FFKuk (ORCPT ); Thu, 6 Jun 2013 06:50:40 -0400 Received: from hqnvupgp07.nvidia.com (Not Verified[216.228.121.13]) by hqemgate04.nvidia.com id ; Thu, 06 Jun 2013 03:50:28 -0700 Received: from hqemhub03.nvidia.com ([172.20.12.94]) by hqnvupgp07.nvidia.com (PGP Universal service); Thu, 06 Jun 2013 03:49:32 -0700 X-PGP-Universal: processed; by hqnvupgp07.nvidia.com on Thu, 06 Jun 2013 03:49:32 -0700 Received: from hqnvemgw01.nvidia.com (172.20.150.20) by HQEMHUB03.nvidia.com (172.20.150.15) with Microsoft SMTP Server id 8.3.298.1; Thu, 6 Jun 2013 03:50:15 -0700 Received: from sc-daphne.nvidia.com (Not Verified[172.20.232.60]) by hqnvemgw01.nvidia.com with MailMarshal (v7,1,2,5326) id ; Thu, 06 Jun 2013 03:50:15 -0700 Received: from tbergstrom-lnx.nvidia.com (tbergstrom-lnx.nvidia.com [10.21.24.170]) by sc-daphne.nvidia.com (8.13.8+Sun/8.8.8) with ESMTP id r56AnSdn023591; Thu, 6 Jun 2013 03:50:13 -0700 (PDT) From: Peter De Schrijver To: Peter De Schrijver CC: , , Stephen Warren , Prashant Gaikwad , Thierry Reding , , Subject: [PATCH v2 2/4] clk: tegra: override bits for Tegra114 PLLM Date: Thu, 6 Jun 2013 13:47:29 +0300 Message-ID: <1370515677-6807-3-git-send-email-pdeschrijver@nvidia.com> X-Mailer: git-send-email 1.7.7.rc0.72.g4b5ea.dirty In-Reply-To: <1370515677-6807-1-git-send-email-pdeschrijver@nvidia.com> References: <1370515677-6807-1-git-send-email-pdeschrijver@nvidia.com> X-NVConfidentiality: public MIME-Version: 1.0 Sender: linux-tegra-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: linux-tegra@vger.kernel.org Define override bits for Tegra114 PLLM. Signed-off-by: Peter De Schrijver --- drivers/clk/tegra/clk-tegra114.c | 9 +++++++++ 1 files changed, 9 insertions(+), 0 deletions(-) diff --git a/drivers/clk/tegra/clk-tegra114.c b/drivers/clk/tegra/clk-tegra114.c index d29ad1d..5b61a51 100644 --- a/drivers/clk/tegra/clk-tegra114.c +++ b/drivers/clk/tegra/clk-tegra114.c @@ -254,6 +254,10 @@ /* Tegra CPU clock and reset control regs */ #define CLK_RST_CONTROLLER_CPU_CMPLX_STATUS 0x470 +/* PLLM override registers */ +#define PMC_PLLM_WB0_OVERRIDE 0x1dc +#define PMC_PLLM_WB0_OVERRIDE_2 0x2b0 + static int periph_clk_enb_refcnt[CLK_OUT_ENB_NUM * 32]; static void __iomem *clk_base; @@ -398,10 +402,13 @@ static struct tegra_clk_pll_params pll_c3_params = { static struct div_nmp pllm_nmp = { .divm_shift = 0, .divm_width = 8, + .override_divm_shift = 0, .divn_shift = 8, .divn_width = 8, + .override_divn_shift = 8, .divp_shift = 20, .divp_width = 1, + .override_divp_shift = 27, }; static struct pdiv_map pllm_p[] = { @@ -434,6 +441,8 @@ static struct tegra_clk_pll_params pll_m_params = { .max_p = 2, .pdiv_tohw = pllm_p, .div_nmp = &pllm_nmp, + .pmc_divnm_reg = PMC_PLLM_WB0_OVERRIDE, + .pmc_divp_reg = PMC_PLLM_WB0_OVERRIDE_2, }; static struct div_nmp pllp_nmp = {