From patchwork Wed Apr 3 11:32:30 2013 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Joseph Lo X-Patchwork-Id: 233415 Return-Path: X-Original-To: incoming@patchwork.ozlabs.org Delivered-To: patchwork-incoming@bilbo.ozlabs.org Received: from vger.kernel.org (vger.kernel.org [209.132.180.67]) by ozlabs.org (Postfix) with ESMTP id C9B9B2C00A8 for ; Wed, 3 Apr 2013 22:32:54 +1100 (EST) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1761661Ab3DCLcx (ORCPT ); Wed, 3 Apr 2013 07:32:53 -0400 Received: from hqemgate04.nvidia.com ([216.228.121.35]:2592 "EHLO hqemgate04.nvidia.com" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1761639Ab3DCLcx (ORCPT ); Wed, 3 Apr 2013 07:32:53 -0400 Received: from hqnvupgp08.nvidia.com (Not Verified[216.228.121.13]) by hqemgate04.nvidia.com id ; Wed, 03 Apr 2013 04:32:38 -0700 Received: from hqemhub01.nvidia.com ([172.20.12.94]) by hqnvupgp08.nvidia.com (PGP Universal service); Wed, 03 Apr 2013 04:32:38 -0700 X-PGP-Universal: processed; by hqnvupgp08.nvidia.com on Wed, 03 Apr 2013 04:32:38 -0700 Received: from jlo-ubuntu-64.nvidia.com (172.20.144.16) by hqemhub01.nvidia.com (172.20.150.30) with Microsoft SMTP Server (TLS) id 8.3.298.1; Wed, 3 Apr 2013 04:32:37 -0700 From: Joseph Lo To: Stephen Warren CC: , , Joseph Lo , John Stultz , Thomas Gleixner Subject: [PATCH] clocksource: tegra: enable arch_timer Date: Wed, 3 Apr 2013 19:32:30 +0800 Message-ID: <1364988750-25058-1-git-send-email-josephl@nvidia.com> X-Mailer: git-send-email 1.8.2 X-NVConfidentiality: public MIME-Version: 1.0 Sender: linux-tegra-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: linux-tegra@vger.kernel.org Architected timer is the local timer for Cortex-A15. Adding the support for Tegra. Cc: John Stultz Cc: Thomas Gleixner Signed-off-by: Joseph Lo Tested-by: Stephen Warren --- drivers/clocksource/tegra20_timer.c | 7 +++++-- 1 file changed, 5 insertions(+), 2 deletions(-) diff --git a/drivers/clocksource/tegra20_timer.c b/drivers/clocksource/tegra20_timer.c index ae877b0..e443f44 100644 --- a/drivers/clocksource/tegra20_timer.c +++ b/drivers/clocksource/tegra20_timer.c @@ -30,6 +30,7 @@ #include #include #include +#include #define RTC_SECONDS 0x08 #define RTC_SHADOW_SECONDS 0x0c @@ -200,8 +201,6 @@ static void __init tegra20_init_timer(struct device_node *np) WARN(1, "Unknown clock rate"); } - setup_sched_clock(tegra_read_sched_clock, 32, 1000000); - if (clocksource_mmio_init(timer_reg_base + TIMERUS_CNTR_1US, "timer_us", 1000000, 300, 32, clocksource_mmio_readl_up)) { pr_err("Failed to register clocksource\n"); @@ -218,6 +217,10 @@ static void __init tegra20_init_timer(struct device_node *np) tegra_clockevent.irq = tegra_timer_irq.irq; clockevents_config_and_register(&tegra_clockevent, 1000000, 0x1, 0x1fffffff); + if (arch_timer_of_register()) + setup_sched_clock(tegra_read_sched_clock, 32, 1000000); + else + arch_timer_sched_clock_init(); } CLOCKSOURCE_OF_DECLARE(tegra20_timer, "nvidia,tegra20-timer", tegra20_init_timer);