From patchwork Wed Mar 20 13:44:27 2013 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Laxman Dewangan X-Patchwork-Id: 229385 Return-Path: X-Original-To: incoming@patchwork.ozlabs.org Delivered-To: patchwork-incoming@bilbo.ozlabs.org Received: from vger.kernel.org (vger.kernel.org [209.132.180.67]) by ozlabs.org (Postfix) with ESMTP id 639722C00C5 for ; Thu, 21 Mar 2013 00:48:58 +1100 (EST) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1754776Ab3CTNs3 (ORCPT ); Wed, 20 Mar 2013 09:48:29 -0400 Received: from hqemgate04.nvidia.com ([216.228.121.35]:9969 "EHLO hqemgate04.nvidia.com" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1753515Ab3CTNsC (ORCPT ); Wed, 20 Mar 2013 09:48:02 -0400 Received: from hqnvupgp08.nvidia.com (Not Verified[216.228.121.13]) by hqemgate04.nvidia.com id ; Wed, 20 Mar 2013 06:47:48 -0700 Received: from hqemhub01.nvidia.com ([172.17.108.22]) by hqnvupgp08.nvidia.com (PGP Universal service); Wed, 20 Mar 2013 06:40:37 -0700 X-PGP-Universal: processed; by hqnvupgp08.nvidia.com on Wed, 20 Mar 2013 06:40:37 -0700 Received: from hqnvemgw01.nvidia.com (172.20.150.20) by hqemhub01.nvidia.com (172.20.150.30) with Microsoft SMTP Server id 8.3.298.1; Wed, 20 Mar 2013 06:47:50 -0700 Received: from thelma.nvidia.com (Not Verified[172.16.212.77]) by hqnvemgw01.nvidia.com with MailMarshal (v7,1,2,5326) id ; Wed, 20 Mar 2013 06:47:51 -0700 Received: from ldewangan-ubuntu.nvidia.com ([10.19.65.30]) by thelma.nvidia.com (8.13.8+Sun/8.8.8) with ESMTP id r2KDljii019114; Wed, 20 Mar 2013 06:47:48 -0700 (PDT) From: Laxman Dewangan To: CC: , , , , , Laxman Dewangan Subject: [PATCH 1/4] ARM: tegra: enable Tegra114 based platform PMICs Date: Wed, 20 Mar 2013 19:14:27 +0530 Message-ID: <1363787070-14801-2-git-send-email-ldewangan@nvidia.com> X-Mailer: git-send-email 1.7.1.1 In-Reply-To: <1363787070-14801-1-git-send-email-ldewangan@nvidia.com> References: <1363787070-14801-1-git-send-email-ldewangan@nvidia.com> MIME-Version: 1.0 Sender: linux-tegra-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: linux-tegra@vger.kernel.org NVIDIA's Tegra114 have two reference platform, Dalmore and Pluto. Dalmore uses the following PMICs: - TPS65913 as primary PMIC. - TPS65090 as secondary PMIC used for switch regulators and battery charging. - TPS51632 for cpu regulator. Pluto uses the TPS65913 as the PMIC. Enable config variable of these PMICs for Dalomore and Pluto. Signed-off-by: Laxman Dewangan --- arch/arm/configs/tegra_defconfig | 7 +++++++ 1 files changed, 7 insertions(+), 0 deletions(-) diff --git a/arch/arm/configs/tegra_defconfig b/arch/arm/configs/tegra_defconfig index aba4881..34b9342 100644 --- a/arch/arm/configs/tegra_defconfig +++ b/arch/arm/configs/tegra_defconfig @@ -126,6 +126,7 @@ CONFIG_SPI=y CONFIG_SPI_TEGRA20_SFLASH=y CONFIG_SPI_TEGRA20_SLINK=y CONFIG_GPIO_PCA953X_IRQ=y +CONFIG_GPIO_PALMAS=y CONFIG_GPIO_TPS6586X=y CONFIG_GPIO_TPS65910=y CONFIG_POWER_SUPPLY=y @@ -136,12 +137,17 @@ CONFIG_SENSORS_LM90=y CONFIG_MFD_TPS6586X=y CONFIG_MFD_TPS65910=y CONFIG_MFD_MAX8907=y +CONFIG_MFD_TPS65090=y +CONFIG_MFD_PALMAS=y CONFIG_REGULATOR=y CONFIG_REGULATOR_FIXED_VOLTAGE=y CONFIG_REGULATOR_VIRTUAL_CONSUMER=y CONFIG_REGULATOR_GPIO=y CONFIG_REGULATOR_MAX8907=y +CONFIG_REGULATOR_PALMAS=y +CONFIG_REGULATOR_TPS51632=y CONFIG_REGULATOR_TPS62360=y +CONFIG_REGULATOR_TPS65090=y CONFIG_REGULATOR_TPS6586X=y CONFIG_REGULATOR_TPS65910=y CONFIG_MEDIA_SUPPORT=y @@ -191,6 +197,7 @@ CONFIG_RTC_INTF_SYSFS=y CONFIG_RTC_INTF_PROC=y CONFIG_RTC_INTF_DEV=y CONFIG_RTC_DRV_MAX8907=y +CONFIG_RTC_DRV_PALMAS=y CONFIG_RTC_DRV_TPS6586X=y CONFIG_RTC_DRV_TPS65910=y CONFIG_RTC_DRV_EM3027=y