From patchwork Thu Mar 14 15:27:05 2013 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Thierry Reding X-Patchwork-Id: 227704 Return-Path: X-Original-To: incoming@patchwork.ozlabs.org Delivered-To: patchwork-incoming@bilbo.ozlabs.org Received: from vger.kernel.org (vger.kernel.org [209.132.180.67]) by ozlabs.org (Postfix) with ESMTP id 34CA02C00B2 for ; Fri, 15 Mar 2013 02:27:20 +1100 (EST) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1757489Ab3CNP1T (ORCPT ); Thu, 14 Mar 2013 11:27:19 -0400 Received: from moutng.kundenserver.de ([212.227.17.9]:53016 "EHLO moutng.kundenserver.de" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1755831Ab3CNP1S (ORCPT ); Thu, 14 Mar 2013 11:27:18 -0400 Received: from mailbox.adnet.avionic-design.de (mailbox.avionic-design.de [109.75.18.3]) by mrelayeu.kundenserver.de (node=mrbap4) with ESMTP (Nemesis) id 0MVd4p-1UFEye2qRr-00YiKH; Thu, 14 Mar 2013 16:27:11 +0100 Received: from localhost (localhost [127.0.0.1]) by mailbox.adnet.avionic-design.de (Postfix) with ESMTP id 015B428B016F; Thu, 14 Mar 2013 16:27:10 +0100 (CET) X-Virus-Scanned: amavisd-new at avionic-design.de Received: from mailbox.adnet.avionic-design.de ([127.0.0.1]) by localhost (mailbox.avionic-design.de [127.0.0.1]) (amavisd-new, port 10024) with ESMTP id JHfnY3+cGru4; Thu, 14 Mar 2013 16:27:05 +0100 (CET) Received: from mailman.adnet.avionic-design.de (mailman.adnet.avionic-design.de [172.20.31.172]) by mailbox.adnet.avionic-design.de (Postfix) with ESMTP id B4D642A28112; Thu, 14 Mar 2013 16:27:05 +0100 (CET) Received: from localhost (avionic-0098.adnet.avionic-design.de [172.20.31.233]) by mailman.adnet.avionic-design.de (Postfix) with ESMTP id 2B54A1001A2; Thu, 14 Mar 2013 16:27:03 +0100 (CET) From: Thierry Reding To: Stephen Warren , Mike Turquette Cc: Prashant Gaikwad , Peter De Schrijver , linux-tegra@vger.kernel.org Subject: [PATCH] clk: tegra: Allow PLLE training to succeed Date: Thu, 14 Mar 2013 16:27:05 +0100 Message-Id: <1363274825-2439-1-git-send-email-thierry.reding@avionic-design.de> X-Mailer: git-send-email 1.8.1.5 X-Provags-ID: V02:K0:4C/9h5xGOEaJ8HEDR0DADeOdpl/b80EhDvDmCE5HPmg BS0wcidt5Wwji5jFyWAQ4bdg2lVohbQci2sWeZ94ek/cmFhlGJ gRkL3TBFpotY/4ZdJ380zXK1O4BLGy1PBgmfVPxAkgnpqZuOzI P1KJGMuNaI/JLWobc1LINnfpyTCn4edrm8RReIzQ6RFOF4/SyB PQ3o6Z7lalV+0S8EQu0HNwrcv13puJOeHFIHof2dWvp7jQgYXg sLfuQ3BlZ6vgudvVLlZbtUKwcgjnjgvrJP21XKrpoWNp8XiGpT Eshj2MquidjDulxZnkohsNjTeZ1o1GAa9HThKRyubJVhgBzAlg x5UpuYINrPi7Kf/TA1E8oVDZnuBCcVHYXo46Wsu1kZQQgKD9HI hGziAuyd/4ci0Yueo8sMAeT9FBe0SO94+c9I/x6ECF143D4q5b +UI6U Sender: linux-tegra-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: linux-tegra@vger.kernel.org Under some circumstances the PLLE needs to be retrained, in which case access to the PMC registers is required. Fix this by passing a pointer to the PMC registers instead of NULL when registering the PLLE clock. Signed-off-by: Thierry Reding Acked-By: Peter De Schrijver --- drivers/clk/tegra/clk-tegra20.c | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/drivers/clk/tegra/clk-tegra20.c b/drivers/clk/tegra/clk-tegra20.c index b92d48b..bf19400 100644 --- a/drivers/clk/tegra/clk-tegra20.c +++ b/drivers/clk/tegra/clk-tegra20.c @@ -703,7 +703,7 @@ static void tegra20_pll_init(void) clks[pll_a_out0] = clk; /* PLLE */ - clk = tegra_clk_register_plle("pll_e", "pll_ref", clk_base, NULL, + clk = tegra_clk_register_plle("pll_e", "pll_ref", clk_base, pmc_base, 0, 100000000, &pll_e_params, 0, pll_e_freq_table, NULL); clk_register_clkdev(clk, "pll_e", NULL);