From patchwork Wed Aug 15 09:22:30 2012 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Joseph Lo X-Patchwork-Id: 177586 Return-Path: X-Original-To: incoming@patchwork.ozlabs.org Delivered-To: patchwork-incoming@bilbo.ozlabs.org Received: from vger.kernel.org (vger.kernel.org [209.132.180.67]) by ozlabs.org (Postfix) with ESMTP id 56F1E2C009B for ; Wed, 15 Aug 2012 19:23:03 +1000 (EST) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1751549Ab2HOJXB (ORCPT ); Wed, 15 Aug 2012 05:23:01 -0400 Received: from hqemgate04.nvidia.com ([216.228.121.35]:7870 "EHLO hqemgate04.nvidia.com" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1750923Ab2HOJXA (ORCPT ); Wed, 15 Aug 2012 05:23:00 -0400 Received: from hqnvupgp06.nvidia.com (Not Verified[216.228.121.13]) by hqemgate04.nvidia.com id ; Wed, 15 Aug 2012 02:22:11 -0700 Received: from hqemhub02.nvidia.com ([172.17.108.22]) by hqnvupgp06.nvidia.com (PGP Universal service); Wed, 15 Aug 2012 02:22:51 -0700 X-PGP-Universal: processed; by hqnvupgp06.nvidia.com on Wed, 15 Aug 2012 02:22:51 -0700 Received: from localhost.localdomain (172.20.144.16) by hqemhub02.nvidia.com (172.20.150.31) with Microsoft SMTP Server (TLS) id 8.3.264.0; Wed, 15 Aug 2012 02:22:50 -0700 From: Joseph Lo To: Stephen Warren , Olof Johansson , Colin Cross CC: , , Joseph Lo Subject: [PATCH V2 2/6] ARM: tegra: replace the CPU CAR access code by tegra_cpu_car_ops Date: Wed, 15 Aug 2012 17:22:30 +0800 Message-ID: <1345022554-26292-3-git-send-email-josephl@nvidia.com> X-Mailer: git-send-email 1.7.0.4 In-Reply-To: <1345022554-26292-1-git-send-email-josephl@nvidia.com> References: <1345022554-26292-1-git-send-email-josephl@nvidia.com> X-NVConfidentiality: public MIME-Version: 1.0 Sender: linux-tegra-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: linux-tegra@vger.kernel.org Replacing the code that directly access to CAR registers with tegra_cpu_car_ops. This ops hides CPU CAR access inside and provides control interface for it. Signed-off-by: Joseph Lo --- arch/arm/mach-tegra/platsmp.c | 29 +++++------------------------ 1 files changed, 5 insertions(+), 24 deletions(-) diff --git a/arch/arm/mach-tegra/platsmp.c b/arch/arm/mach-tegra/platsmp.c index 1a208db..96ed171 100644 --- a/arch/arm/mach-tegra/platsmp.c +++ b/arch/arm/mach-tegra/platsmp.c @@ -31,6 +31,7 @@ #include "fuse.h" #include "flowctrl.h" #include "reset.h" +#include "tegra_cpu_car.h" extern void tegra_secondary_startup(void); @@ -38,17 +39,6 @@ static void __iomem *scu_base = IO_ADDRESS(TEGRA_ARM_PERIF_BASE); #define EVP_CPU_RESET_VECTOR \ (IO_ADDRESS(TEGRA_EXCEPTION_VECTORS_BASE) + 0x100) -#define CLK_RST_CONTROLLER_CLK_CPU_CMPLX \ - (IO_ADDRESS(TEGRA_CLK_RESET_BASE) + 0x4c) -#define CLK_RST_CONTROLLER_RST_CPU_CMPLX_SET \ - (IO_ADDRESS(TEGRA_CLK_RESET_BASE) + 0x340) -#define CLK_RST_CONTROLLER_RST_CPU_CMPLX_CLR \ - (IO_ADDRESS(TEGRA_CLK_RESET_BASE) + 0x344) -#define CLK_RST_CONTROLLER_CLK_CPU_CMPLX_CLR \ - (IO_ADDRESS(TEGRA_CLK_RESET_BASE) + 0x34c) - -#define CPU_CLOCK(cpu) (0x1<<(8+cpu)) -#define CPU_RESET(cpu) (0x1111ul<<(cpu)) void __cpuinit platform_secondary_init(unsigned int cpu) { @@ -63,13 +53,8 @@ void __cpuinit platform_secondary_init(unsigned int cpu) static int tegra20_power_up_cpu(unsigned int cpu) { - u32 reg; - /* Enable the CPU clock. */ - reg = readl(CLK_RST_CONTROLLER_CLK_CPU_CMPLX); - writel(reg & ~CPU_CLOCK(cpu), CLK_RST_CONTROLLER_CLK_CPU_CMPLX); - barrier(); - reg = readl(CLK_RST_CONTROLLER_CLK_CPU_CMPLX); + tegra_enable_cpu_clock(cpu); /* Clear flow controller CSR. */ flowctrl_write_cpu_csr(cpu, 0); @@ -79,7 +64,6 @@ static int tegra20_power_up_cpu(unsigned int cpu) static int tegra30_power_up_cpu(unsigned int cpu) { - u32 reg; int ret, pwrgateid; unsigned long timeout; @@ -103,8 +87,7 @@ static int tegra30_power_up_cpu(unsigned int cpu) } /* CPU partition is powered. Enable the CPU clock. */ - writel(CPU_CLOCK(cpu), CLK_RST_CONTROLLER_CLK_CPU_CMPLX_CLR); - reg = readl(CLK_RST_CONTROLLER_CLK_CPU_CMPLX_CLR); + tegra_enable_cpu_clock(cpu); udelay(10); /* Remove I/O clamps. */ @@ -128,8 +111,7 @@ int __cpuinit boot_secondary(unsigned int cpu, struct task_struct *idle) * via the flow controller). This will have no effect on first boot * of the CPU since it should already be in reset. */ - writel(CPU_RESET(cpu), CLK_RST_CONTROLLER_RST_CPU_CMPLX_SET); - dmb(); + tegra_put_cpu_in_reset(cpu); /* * Unhalt the CPU. If the flow controller was used to power-gate the @@ -155,8 +137,7 @@ int __cpuinit boot_secondary(unsigned int cpu, struct task_struct *idle) goto done; /* Take the CPU out of reset. */ - writel(CPU_RESET(cpu), CLK_RST_CONTROLLER_RST_CPU_CMPLX_CLR); - wmb(); + tegra_cpu_out_of_reset(cpu); done: return status; }