From patchwork Tue Aug 14 08:07:22 2012 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Joseph Lo X-Patchwork-Id: 177177 Return-Path: X-Original-To: incoming@patchwork.ozlabs.org Delivered-To: patchwork-incoming@bilbo.ozlabs.org Received: from vger.kernel.org (vger.kernel.org [209.132.180.67]) by ozlabs.org (Postfix) with ESMTP id 6AD1A2C0086 for ; Tue, 14 Aug 2012 18:08:00 +1000 (EST) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1753746Ab2HNIHy (ORCPT ); Tue, 14 Aug 2012 04:07:54 -0400 Received: from hqemgate04.nvidia.com ([216.228.121.35]:15252 "EHLO hqemgate04.nvidia.com" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1753844Ab2HNIHv (ORCPT ); Tue, 14 Aug 2012 04:07:51 -0400 Received: from hqnvupgp08.nvidia.com (Not Verified[216.228.121.13]) by hqemgate04.nvidia.com id ; Tue, 14 Aug 2012 01:07:08 -0700 Received: from hqemhub02.nvidia.com ([172.17.108.22]) by hqnvupgp08.nvidia.com (PGP Universal service); Tue, 14 Aug 2012 01:07:48 -0700 X-PGP-Universal: processed; by hqnvupgp08.nvidia.com on Tue, 14 Aug 2012 01:07:48 -0700 Received: from localhost.localdomain (172.20.144.16) by hqemhub02.nvidia.com (172.20.150.31) with Microsoft SMTP Server (TLS) id 8.3.264.0; Tue, 14 Aug 2012 01:07:46 -0700 From: Joseph Lo To: Stephen Warren , Olof Johansson , Colin Cross CC: , , Joseph Lo Subject: [PATCH 3/5] ARM: tegra: clean up the common assembly macros into sleep.h Date: Tue, 14 Aug 2012 16:07:22 +0800 Message-ID: <1344931644-3927-4-git-send-email-josephl@nvidia.com> X-Mailer: git-send-email 1.7.0.4 In-Reply-To: <1344931644-3927-1-git-send-email-josephl@nvidia.com> References: <1344931644-3927-1-git-send-email-josephl@nvidia.com> X-NVConfidentiality: public MIME-Version: 1.0 Sender: linux-tegra-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: linux-tegra@vger.kernel.org There are some common macros for Tegra low-level assembly code. Clean up them into one header file and move the definitions that will be re-used into it as well. Signed-off-by: Joseph Lo --- arch/arm/mach-tegra/headsmp.S | 6 +--- arch/arm/mach-tegra/sleep.S | 33 +----------------------- arch/arm/mach-tegra/sleep.h | 56 +++++++++++++++++++++++++++++++++++++++++ 3 files changed, 58 insertions(+), 37 deletions(-) create mode 100644 arch/arm/mach-tegra/sleep.h diff --git a/arch/arm/mach-tegra/headsmp.S b/arch/arm/mach-tegra/headsmp.S index fef9c2c..6addc78 100644 --- a/arch/arm/mach-tegra/headsmp.S +++ b/arch/arm/mach-tegra/headsmp.S @@ -7,17 +7,13 @@ #include "flowctrl.h" #include "reset.h" +#include "sleep.h" #define APB_MISC_GP_HIDREV 0x804 #define PMC_SCRATCH41 0x140 #define RESET_DATA(x) ((TEGRA_RESET_##x)*4) - .macro mov32, reg, val - movw \reg, #:lower16:\val - movt \reg, #:upper16:\val - .endm - .section ".text.head", "ax" __CPUINIT diff --git a/arch/arm/mach-tegra/sleep.S b/arch/arm/mach-tegra/sleep.S index d29b156..ea81554 100644 --- a/arch/arm/mach-tegra/sleep.S +++ b/arch/arm/mach-tegra/sleep.S @@ -29,36 +29,5 @@ #include #include "flowctrl.h" +#include "sleep.h" -#define TEGRA_FLOW_CTRL_VIRT (TEGRA_FLOW_CTRL_BASE - IO_PPSB_PHYS \ - + IO_PPSB_VIRT) - -/* returns the offset of the flow controller halt register for a cpu */ -.macro cpu_to_halt_reg rd, rcpu - cmp \rcpu, #0 - subne \rd, \rcpu, #1 - movne \rd, \rd, lsl #3 - addne \rd, \rd, #0x14 - moveq \rd, #0 -.endm - -/* returns the offset of the flow controller csr register for a cpu */ -.macro cpu_to_csr_reg rd, rcpu - cmp \rcpu, #0 - subne \rd, \rcpu, #1 - movne \rd, \rd, lsl #3 - addne \rd, \rd, #0x18 - moveq \rd, #8 -.endm - -/* returns the ID of the current processor */ -.macro cpu_id, rd - mrc p15, 0, \rd, c0, c0, 5 - and \rd, \rd, #0xF -.endm - -/* loads a 32-bit value into a register without a data access */ -.macro mov32, reg, val - movw \reg, #:lower16:\val - movt \reg, #:upper16:\val -.endm diff --git a/arch/arm/mach-tegra/sleep.h b/arch/arm/mach-tegra/sleep.h new file mode 100644 index 0000000..d0c7a8b --- /dev/null +++ b/arch/arm/mach-tegra/sleep.h @@ -0,0 +1,56 @@ +/* + * Copyright (c) 2010-2012, NVIDIA Corporation. All rights reserved. + * + * This program is free software; you can redistribute it and/or modify it + * under the terms and conditions of the GNU General Public License, + * version 2, as published by the Free Software Foundation. + * + * This program is distributed in the hope it will be useful, but WITHOUT + * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or + * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for + * more details. + * + * You should have received a copy of the GNU General Public License + * along with this program. If not, see . + */ + +#ifndef __MACH_TEGRA_SLEEP_H +#define __MACH_TEGRA_SLEEP_H + +#include + +#define TEGRA_FLOW_CTRL_VIRT (TEGRA_FLOW_CTRL_BASE - IO_PPSB_PHYS \ + + IO_PPSB_VIRT) + +#ifdef __ASSEMBLY__ +/* returns the offset of the flow controller halt register for a cpu */ +.macro cpu_to_halt_reg rd, rcpu + cmp \rcpu, #0 + subne \rd, \rcpu, #1 + movne \rd, \rd, lsl #3 + addne \rd, \rd, #0x14 + moveq \rd, #0 +.endm + +/* returns the offset of the flow controller csr register for a cpu */ +.macro cpu_to_csr_reg rd, rcpu + cmp \rcpu, #0 + subne \rd, \rcpu, #1 + movne \rd, \rd, lsl #3 + addne \rd, \rd, #0x18 + moveq \rd, #8 +.endm + +/* returns the ID of the current processor */ +.macro cpu_id, rd + mrc p15, 0, \rd, c0, c0, 5 + and \rd, \rd, #0xF +.endm + +/* loads a 32-bit value into a register without a data access */ +.macro mov32, reg, val + movw \reg, #:lower16:\val + movt \reg, #:upper16:\val +.endm +#endif +#endif