From patchwork Thu Jan 31 09:24:03 2019 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Joseph Lo X-Patchwork-Id: 1034071 Return-Path: X-Original-To: incoming@patchwork.ozlabs.org Delivered-To: patchwork-incoming@bilbo.ozlabs.org Authentication-Results: ozlabs.org; spf=none (mailfrom) smtp.mailfrom=vger.kernel.org (client-ip=209.132.180.67; helo=vger.kernel.org; envelope-from=linux-tegra-owner@vger.kernel.org; receiver=) Authentication-Results: ozlabs.org; dmarc=pass (p=none dis=none) header.from=nvidia.com Authentication-Results: ozlabs.org; dkim=pass (2048-bit key; unprotected) header.d=nvidia.com header.i=@nvidia.com header.b="UWDR0ZHW"; dkim-atps=neutral Received: from vger.kernel.org (vger.kernel.org [209.132.180.67]) by ozlabs.org (Postfix) with ESMTP id 43qvv62pH2z9sBQ for ; Thu, 31 Jan 2019 20:24:18 +1100 (AEDT) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1727546AbfAaJYR (ORCPT ); Thu, 31 Jan 2019 04:24:17 -0500 Received: from hqemgate14.nvidia.com ([216.228.121.143]:4680 "EHLO hqemgate14.nvidia.com" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1727501AbfAaJYR (ORCPT ); Thu, 31 Jan 2019 04:24:17 -0500 Received: from hqpgpgate101.nvidia.com (Not Verified[216.228.121.13]) by hqemgate14.nvidia.com (using TLS: TLSv1.2, DES-CBC3-SHA) id ; Thu, 31 Jan 2019 01:24:18 -0800 Received: from hqmail.nvidia.com ([172.20.161.6]) by hqpgpgate101.nvidia.com (PGP Universal service); Thu, 31 Jan 2019 01:24:16 -0800 X-PGP-Universal: processed; by hqpgpgate101.nvidia.com on Thu, 31 Jan 2019 01:24:16 -0800 Received: from HQMAIL102.nvidia.com (172.18.146.10) by HQMAIL107.nvidia.com (172.20.187.13) with Microsoft SMTP Server (TLS) id 15.0.1395.4; Thu, 31 Jan 2019 09:24:16 +0000 Received: from hqnvemgw02.nvidia.com (172.16.227.111) by HQMAIL102.nvidia.com (172.18.146.10) with Microsoft SMTP Server (TLS) id 15.0.1395.4 via Frontend Transport; Thu, 31 Jan 2019 09:24:16 +0000 Received: from josephl-linux.nvidia.com (Not Verified[10.19.108.132]) by hqnvemgw02.nvidia.com with Trustwave SEG (v7, 5, 8, 10121) id ; Thu, 31 Jan 2019 01:24:16 -0800 From: Joseph Lo To: Thierry Reding , Jonathan Hunter CC: , , Joseph Lo Subject: [PATCH V4 0/7] Add CPUidle support for Tegra210 Date: Thu, 31 Jan 2019 17:24:03 +0800 Message-ID: <20190131092410.28222-1-josephl@nvidia.com> X-Mailer: git-send-email 2.20.1 MIME-Version: 1.0 X-NVConfidentiality: public DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=nvidia.com; s=n1; t=1548926658; bh=ENHYVgcqOP6xBR3gwZRGINRwAQgtBFPqvTozpD28GI0=; h=X-PGP-Universal:From:To:CC:Subject:Date:Message-ID:X-Mailer: MIME-Version:X-NVConfidentiality:Content-Transfer-Encoding: Content-Type; b=UWDR0ZHWDVrmOB29Q3eKa4JCgvg3cMPVudpjVQBwfNWBl1+muV0kBfpnG/MomjvOm GQJ0oK1I9QLon1rZdv7CuhWg8GhOumDogzJi06QBhlxcMEJwTejR5fu5ZYhriMwGWK /XF8RVsDXSuL4ujbtG6ETOCpFCDS4FtUYTXGUvbhCVkrA5+sPVmhFjdrgAcF5ydek+ FLEsrehk9dwVtwMflm9u9mI6aC4oSwHUw4OnBG6o8ybYOxzTOgcXz/JNZNXP3Du78j DqqIaH67QbgmiuK2nZMCvzmnePZHd8jT0K2Krzx+JPUtBPeeCbgws3KGGbGtaWY04J V6/ETX0jrS4tA== Sender: linux-tegra-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: linux-tegra@vger.kernel.org This patch series adds CPUidle support for Tegra210, which supports power-down state (C7) for CPU cores. And due to arch timer cannot work across CPU core power-down and power on reset signal event. We introduce Tegra210 timer driver to work as clock event device. So it can be the wake-up source of CPU cores when they idled in the power-down state. Fixed in V4: * merge timer-tegra210.c into timer-tegra20.c * add a new patch to select TEGRA_TIMER by default for Tegra210 Fixed in V3: * use timer-of API for Tegra210 timer driver Fixed in V2: * list all the timer IRQs in the binding doc and dts file * add error clean-up code in timer driver * add entry-latency-us and exit-latency-us properties for idle-states DT node Joseph Lo (7): dt-bindings: timer: add Tegra210 timer clocksource: tegra: add Tegra210 timer support soc/tegra: default select TEGRA_TIMER for Tegra210 arm64: dts: tegra210: fix timer node arm64: dts: tegra210: add CPU idle states properties arm64: dts: tegra210-p2180: Enable CPU idle support arm64: dts: tegra210-smaug: Enable CPU idle support .../bindings/timer/nvidia,tegra210-timer.txt | 36 ++ .../arm64/boot/dts/nvidia/tegra210-p2180.dtsi | 6 + arch/arm64/boot/dts/nvidia/tegra210-smaug.dts | 7 + arch/arm64/boot/dts/nvidia/tegra210.dtsi | 33 +- drivers/clocksource/Kconfig | 2 +- drivers/clocksource/timer-tegra20.c | 369 +++++++++++++----- drivers/soc/tegra/Kconfig | 1 + include/linux/cpuhotplug.h | 1 + 8 files changed, 352 insertions(+), 103 deletions(-) create mode 100644 Documentation/devicetree/bindings/timer/nvidia,tegra210-timer.txt