| Message ID | 6d3a4483d22753ba8114304db07756620c66da41.1626176145.git.baruch@tkos.co.il |
|---|---|
| State | Superseded |
| Headers | show |
| Series | [v5,1/4] arm64: dts: ipq6018: correct TCSR block area | expand |
On Tue, Jul 13, 2021 at 02:35:44PM +0300, Baruch Siach wrote: > DT binding for the PWM block in Qualcomm IPQ6018 SoC. > > Signed-off-by: Baruch Siach <baruch@tkos.co.il> > --- > v5: Use qcom,pwm-regs for phandle instead of direct regs (Bjorn > Andersson, Kathiravan T) > > v4: Update the binding example node as well (Rob Herring's bot) > > v3: s/qcom,pwm-ipq6018/qcom,ipq6018-pwm/ (Rob Herring) > > v2: Make #pwm-cells const (Rob Herring) > --- > .../devicetree/bindings/pwm/ipq-pwm.yaml | 55 +++++++++++++++++++ > 1 file changed, 55 insertions(+) > create mode 100644 Documentation/devicetree/bindings/pwm/ipq-pwm.yaml > > diff --git a/Documentation/devicetree/bindings/pwm/ipq-pwm.yaml b/Documentation/devicetree/bindings/pwm/ipq-pwm.yaml > new file mode 100644 > index 000000000000..a07bfe63dc1a > --- /dev/null > +++ b/Documentation/devicetree/bindings/pwm/ipq-pwm.yaml > @@ -0,0 +1,55 @@ > +# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) > +%YAML 1.2 > +--- > +$id: http://devicetree.org/schemas/pwm/ipq-pwm.yaml# > +$schema: http://devicetree.org/meta-schemas/core.yaml# > + > +title: Qualcomm IPQ6018 PWM controller > + > +maintainers: > + - Baruch Siach <baruch@tkos.co.il> > + > +properties: > + "#pwm-cells": > + const: 2 > + > + compatible: > + const: qcom,ipq6018-pwm > + > + qcom,pwm-regs: > + $ref: '/schemas/types.yaml#/definitions/phandle-array' > + maxItems: 1 > + description: | > + phandle link and offset to TCSR block This binding should be a child of the TCSR I think as Bjorn asked. > + > + clocks: > + maxItems: 1 > + > + clock-names: > + const: core > + > +required: > + - "#pwm-cells" > + - compatible > + - qcom,pwm-regs > + - clocks > + - clock-names > + > +additionalProperties: false > + > +examples: > + - | > + #include <dt-bindings/clock/qcom,gcc-ipq6018.h> > + > + soc { > + #address-cells = <2>; > + #size-cells = <2>; > + > + pwm { > + #pwm-cells = <2>; > + compatible = "qcom,ipq6018-pwm"; > + qcom,pwm-regs = <&tcsr_q6 0xa010>; > + clocks = <&gcc GCC_ADSS_PWM_CLK>; > + clock-names = "core"; > + }; > + }; > -- > 2.30.2 > >
diff --git a/Documentation/devicetree/bindings/pwm/ipq-pwm.yaml b/Documentation/devicetree/bindings/pwm/ipq-pwm.yaml new file mode 100644 index 000000000000..a07bfe63dc1a --- /dev/null +++ b/Documentation/devicetree/bindings/pwm/ipq-pwm.yaml @@ -0,0 +1,55 @@ +# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) +%YAML 1.2 +--- +$id: http://devicetree.org/schemas/pwm/ipq-pwm.yaml# +$schema: http://devicetree.org/meta-schemas/core.yaml# + +title: Qualcomm IPQ6018 PWM controller + +maintainers: + - Baruch Siach <baruch@tkos.co.il> + +properties: + "#pwm-cells": + const: 2 + + compatible: + const: qcom,ipq6018-pwm + + qcom,pwm-regs: + $ref: '/schemas/types.yaml#/definitions/phandle-array' + maxItems: 1 + description: | + phandle link and offset to TCSR block + + clocks: + maxItems: 1 + + clock-names: + const: core + +required: + - "#pwm-cells" + - compatible + - qcom,pwm-regs + - clocks + - clock-names + +additionalProperties: false + +examples: + - | + #include <dt-bindings/clock/qcom,gcc-ipq6018.h> + + soc { + #address-cells = <2>; + #size-cells = <2>; + + pwm { + #pwm-cells = <2>; + compatible = "qcom,ipq6018-pwm"; + qcom,pwm-regs = <&tcsr_q6 0xa010>; + clocks = <&gcc GCC_ADSS_PWM_CLK>; + clock-names = "core"; + }; + };
DT binding for the PWM block in Qualcomm IPQ6018 SoC. Signed-off-by: Baruch Siach <baruch@tkos.co.il> --- v5: Use qcom,pwm-regs for phandle instead of direct regs (Bjorn Andersson, Kathiravan T) v4: Update the binding example node as well (Rob Herring's bot) v3: s/qcom,pwm-ipq6018/qcom,ipq6018-pwm/ (Rob Herring) v2: Make #pwm-cells const (Rob Herring) --- .../devicetree/bindings/pwm/ipq-pwm.yaml | 55 +++++++++++++++++++ 1 file changed, 55 insertions(+) create mode 100644 Documentation/devicetree/bindings/pwm/ipq-pwm.yaml