| Message ID | 20260110014524.3379187-3-vz@mleia.com |
|---|---|
| State | Handled Elsewhere |
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bh=9JX/rXLHGcrTabMUzfusMQsBUjz6LX2b1LPrfc/bGPE=; h=From:To:Cc:Subject:Date:In-Reply-To:References:From; b=cEhXN1QIZgsmjPONfJwPPcPwCctX5FxXGpz2NRr+hYCccjhYlegywl6dxSmMeP1ew khhGImm2huMxuQ89q8YbbW8MOygV2WRjMup+NPh+gXxt74R5zpZ7VJBTA4WSGBzQvD Lby2RBAUJNtIMieqrgVdEWG8AwcfOOC6b0DG1VQpXPeLWzMUEsKIHk87XDkz34bnee Bg59pLusbLj7MB1GqZDTrKGeJ3VIM/k4dwls302nkGw+bn3Vg5WIzr/ST5nNinTkFV b7JaChrdgbtMUkOU2E7OHtgoofRU0G1R3aZvCjI2lYBwFLDHORxKwsqYt7RdIM5OVQ ZDyrNm92BzANA== Received: from mail.mleia.com (91-159-24-186.elisa-laajakaista.fi [91.159.24.186]) (using TLSv1.3 with cipher TLS_AES_256_GCM_SHA384 (256/256 bits) key-exchange X25519 server-signature RSA-PSS (2048 bits) server-digest SHA256) (No client certificate requested) by mail.mleia.com (Postfix) with ESMTPSA id 5F3473EB810; Sat, 10 Jan 2026 01:45:43 +0000 (UTC) From: Vladimir Zapolskiy <vz@mleia.com> To: =?utf-8?q?Uwe_Kleine-K=C3=B6nig?= <ukleinek@kernel.org>, Rob Herring <robh@kernel.org>, Krzysztof Kozlowski <krzk+dt@kernel.org>, Conor Dooley <conor+dt@kernel.org>, Frank Li <Frank.Li@nxp.com> Cc: Piotr Wojtaszczyk <piotr.wojtaszczyk@timesys.com>, linux-pwm@vger.kernel.org, devicetree@vger.kernel.org, linux-arm-kernel@lists.infradead.org Subject: [PATCH 2/2] arm: dts: lpc32xx: add interrupts property to Motor Control PWM Date: Sat, 10 Jan 2026 03:45:24 +0200 Message-ID: <20260110014524.3379187-3-vz@mleia.com> X-Mailer: git-send-email 2.43.0 In-Reply-To: <20260110014524.3379187-1-vz@mleia.com> References: <20260110014524.3379187-1-vz@mleia.com> Precedence: bulk X-Mailing-List: linux-pwm@vger.kernel.org List-Id: <linux-pwm.vger.kernel.org> List-Subscribe: <mailto:linux-pwm+subscribe@vger.kernel.org> List-Unsubscribe: <mailto:linux-pwm+unsubscribe@vger.kernel.org> MIME-Version: 1.0 Content-Transfer-Encoding: 8bit X-CRM114-Version: 20100106-BlameMichelson ( TRE 0.8.0 (BSD) ) MR-49551924 X-CRM114-CacheID: sfid-20260110_014544_070900_8715560B X-CRM114-Status: UNSURE ( 9.46 ) X-CRM114-Notice: Please train this message. |
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arm: dts: lpc32xx: Add Motor Control PWM interrupt
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diff --git a/arch/arm/boot/dts/nxp/lpc/lpc32xx.dtsi b/arch/arm/boot/dts/nxp/lpc/lpc32xx.dtsi index 7fa91d1ac9ea..e94df78def18 100644 --- a/arch/arm/boot/dts/nxp/lpc/lpc32xx.dtsi +++ b/arch/arm/boot/dts/nxp/lpc/lpc32xx.dtsi @@ -322,6 +322,7 @@ i2c2: i2c@400a8000 { mpwm: pwm@400e8000 { compatible = "nxp,lpc3220-motor-pwm"; reg = <0x400e8000 0x78>; + interrupts = <3 IRQ_TYPE_LEVEL_LOW>; clocks = <&clk LPC32XX_CLK_MCPWM>; #pwm-cells = <3>; status = "disabled";
Motor Control PWM shares an interrupt line with TIMER4 on MIC interrupt controller, the interrupt serves as period (timer limit), pulse-width (match) and capture event interrupt. Signed-off-by: Vladimir Zapolskiy <vz@mleia.com> --- arch/arm/boot/dts/nxp/lpc/lpc32xx.dtsi | 1 + 1 file changed, 1 insertion(+)