| Message ID | 20251228224907.1729627-3-vz@mleia.com |
|---|---|
| State | Handled Elsewhere |
| Headers | show |
| Series | arm: dts: lpc32xx: Set motor control PWM clock as required one | expand |
On Mon, Dec 29, 2025 at 12:49:07AM +0200, Vladimir Zapolskiy wrote: > Motor Control PWM depends on its own supply clock, the clock gate control > is present in TIMCLK_CTRL1 register. You say it is required, so does that mean this hasn't ever worked? Or it happened to work because something else turned on the clock? > Fixes tag? > Signed-off-by: Vladimir Zapolskiy <vz@mleia.com> > --- > arch/arm/boot/dts/nxp/lpc/lpc32xx.dtsi | 1 + > 1 file changed, 1 insertion(+) > > diff --git a/arch/arm/boot/dts/nxp/lpc/lpc32xx.dtsi b/arch/arm/boot/dts/nxp/lpc/lpc32xx.dtsi > index 39af48470ed5..abd401fda94e 100644 > --- a/arch/arm/boot/dts/nxp/lpc/lpc32xx.dtsi > +++ b/arch/arm/boot/dts/nxp/lpc/lpc32xx.dtsi > @@ -304,6 +304,7 @@ i2c2: i2c@400a8000 { > mpwm: pwm@400e8000 { > compatible = "nxp,lpc3220-motor-pwm"; > reg = <0x400e8000 0x78>; > + clocks = <&clk LPC32XX_CLK_MCPWM>; > #pwm-cells = <3>; > status = "disabled"; > }; > -- > 2.43.0 >
On 12/30/25 19:59, Rob Herring wrote: > On Mon, Dec 29, 2025 at 12:49:07AM +0200, Vladimir Zapolskiy wrote: >> Motor Control PWM depends on its own supply clock, the clock gate control >> is present in TIMCLK_CTRL1 register. > > You say it is required, so does that mean this hasn't ever worked? Or it > happened to work because something else turned on the clock? There is no upstream driver for this particular PWM controller, I'm about to submit one though, and so far I've completed my review of its dt properties. >> > > Fixes tag? It'd make sense, however as I've said above formally there is no fixed runtime bug, if the scope is limited to the upstream only. Fixes: b7d41c937ed7 ("ARM: LPC32xx: Add the motor PWM to base dts file") >> Signed-off-by: Vladimir Zapolskiy <vz@mleia.com> >> --- >> arch/arm/boot/dts/nxp/lpc/lpc32xx.dtsi | 1 + >> 1 file changed, 1 insertion(+) >> >> diff --git a/arch/arm/boot/dts/nxp/lpc/lpc32xx.dtsi b/arch/arm/boot/dts/nxp/lpc/lpc32xx.dtsi >> index 39af48470ed5..abd401fda94e 100644 >> --- a/arch/arm/boot/dts/nxp/lpc/lpc32xx.dtsi >> +++ b/arch/arm/boot/dts/nxp/lpc/lpc32xx.dtsi >> @@ -304,6 +304,7 @@ i2c2: i2c@400a8000 { >> mpwm: pwm@400e8000 { >> compatible = "nxp,lpc3220-motor-pwm"; >> reg = <0x400e8000 0x78>; >> + clocks = <&clk LPC32XX_CLK_MCPWM>; >> #pwm-cells = <3>; >> status = "disabled"; >> }; >> -- >> 2.43.0 >>
diff --git a/arch/arm/boot/dts/nxp/lpc/lpc32xx.dtsi b/arch/arm/boot/dts/nxp/lpc/lpc32xx.dtsi index 39af48470ed5..abd401fda94e 100644 --- a/arch/arm/boot/dts/nxp/lpc/lpc32xx.dtsi +++ b/arch/arm/boot/dts/nxp/lpc/lpc32xx.dtsi @@ -304,6 +304,7 @@ i2c2: i2c@400a8000 { mpwm: pwm@400e8000 { compatible = "nxp,lpc3220-motor-pwm"; reg = <0x400e8000 0x78>; + clocks = <&clk LPC32XX_CLK_MCPWM>; #pwm-cells = <3>; status = "disabled"; };
Motor Control PWM depends on its own supply clock, the clock gate control is present in TIMCLK_CTRL1 register. Signed-off-by: Vladimir Zapolskiy <vz@mleia.com> --- arch/arm/boot/dts/nxp/lpc/lpc32xx.dtsi | 1 + 1 file changed, 1 insertion(+)