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[177.69.253.233]) by smtp.gmail.com with ESMTPSA id a92af1059eb24-11dcaee7076sm12404561c88.4.2025.11.27.16.39.02 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Thu, 27 Nov 2025 16:39:03 -0800 (PST) From: "Rafael V. Volkmer" To: ukleinek@kernel.org Cc: linux-kernel@vger.kernel.org, linux-pwm@vger.kernel.org, rafael.v.volkmer@gmail.com Subject: [PATCH v7 5/9] pwm: tiehrpwm: use FIELD_PREP() for prescaler fields Date: Thu, 27 Nov 2025 21:36:30 -0300 Message-ID: <20251128003634.247529-6-rafael.v.volkmer@gmail.com> X-Mailer: git-send-email 2.43.0 In-Reply-To: <20251128003634.247529-1-rafael.v.volkmer@gmail.com> References: <20251128003634.247529-1-rafael.v.volkmer@gmail.com> Precedence: bulk X-Mailing-List: linux-pwm@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Refactor TBCTL prescaler handling to use GENMASK() and FIELD_PREP() instead of open-coded shifts. Split the prescaler bits into TIEHRPWM_TBCTL_CLKDIV_MASK and TIEHRPWM_TBCTL_HSPCLKDIV_MASK and introduce TIEHRPWM_TBCTL_PRESCALE_MASK to cover both fields. Use FIELD_PREP() in set_prescale_div() to build the prescaler value, and update ehrpwm_modify() to clear and program both fields in a single call. The removed *_SHIFT macros are no longer needed. No functional change intended. Signed-off-by: Rafael V. Volkmer --- drivers/pwm/pwm-tiehrpwm.c | 14 +++++++------- 1 file changed, 7 insertions(+), 7 deletions(-) diff --git a/drivers/pwm/pwm-tiehrpwm.c b/drivers/pwm/pwm-tiehrpwm.c index 4b8b4a9e7379..41af1bf74cbb 100644 --- a/drivers/pwm/pwm-tiehrpwm.c +++ b/drivers/pwm/pwm-tiehrpwm.c @@ -25,7 +25,10 @@ #define TIEHRPWM_TBCTL_PRDLD_SHDW FIELD_PREP(TIEHRPWM_TBCTL_PRDLD, 0) #define TIEHRPWM_TBCTL_PRDLD_IMDT FIELD_PREP(TIEHRPWM_TBCTL_PRDLD, 1) -#define TIEHRPWM_TBCTL_CLKDIV_MASK GENMASK(12, 7) +#define TIEHRPWM_TBCTL_CLKDIV_MASK GENMASK(12, 10) +#define TIEHRPWM_TBCTL_HSPCLKDIV_MASK GENMASK(9, 7) +#define TIEHRPWM_TBCTL_PRESCALE_MASK (TIEHRPWM_TBCTL_CLKDIV_MASK | \ + TIEHRPWM_TBCTL_HSPCLKDIV_MASK) #define TIEHRPWM_TBCTL_CTRMODE_MASK GENMASK(1, 0) #define TIEHRPWM_TBCTL_CTRMODE_UP FIELD_PREP(TIEHRPWM_TBCTL_CTRMODE_MASK, 0) @@ -33,9 +36,6 @@ #define TIEHRPWM_TBCTL_CTRMODE_UPDOWN FIELD_PREP(TIEHRPWM_TBCTL_CTRMODE_MASK, 2) #define TIEHRPWM_TBCTL_CTRMODE_FREEZE FIELD_PREP(TIEHRPWM_TBCTL_CTRMODE_MASK, 3) -#define TIEHRPWM_TBCTL_HSPCLKDIV_SHIFT 7 -#define TIEHRPWM_TBCTL_CLKDIV_SHIFT 10 - #define TIEHRPWM_CLKDIV_MAX 7 #define TIEHRPWM_HSPCLKDIV_MAX 7 @@ -174,8 +174,8 @@ static int set_prescale_div(unsigned long rqst_prescaler, u16 *prescale_div, *prescale_div = (1 << clkdiv) * (hspclkdiv ? (hspclkdiv * 2) : 1); if (*prescale_div >= rqst_prescaler) { - *tb_clk_div = (clkdiv << TIEHRPWM_TBCTL_CLKDIV_SHIFT) | - (hspclkdiv << TIEHRPWM_TBCTL_HSPCLKDIV_SHIFT); + *tb_clk_div = FIELD_PREP(TIEHRPWM_TBCTL_CLKDIV_MASK, clkdiv) | + FIELD_PREP(TIEHRPWM_TBCTL_HSPCLKDIV_MASK, hspclkdiv); return 0; } } @@ -252,7 +252,7 @@ static int ehrpwm_pwm_config(struct pwm_chip *chip, struct pwm_device *pwm, pm_runtime_get_sync(pwmchip_parent(chip)); /* Update clock prescaler values */ - ehrpwm_modify(pc->mmio_base, TIEHRPWM_TBCTL, TIEHRPWM_TBCTL_CLKDIV_MASK, tb_divval); + ehrpwm_modify(pc->mmio_base, TIEHRPWM_TBCTL, TIEHRPWM_TBCTL_PRESCALE_MASK, tb_divval); if (pwm->hwpwm == 1) { /* Channel 1 configured with compare B register */