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[86.139.30.37]) by smtp.gmail.com with ESMTPSA id 5b1f17b1804b1-464f0aac3fdsm238940435e9.1.2025.09.23.07.45.29 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Tue, 23 Sep 2025 07:45:30 -0700 (PDT) From: Biju X-Google-Original-From: Biju To: =?utf-8?q?Uwe_Kleine-K=C3=B6nig?= , Geert Uytterhoeven , Magnus Damm Cc: Biju Das , linux-pwm@vger.kernel.org, linux-kernel@vger.kernel.org, linux-renesas-soc@vger.kernel.org, Prabhakar Mahadev Lad , Biju Das , Tommaso Merciai Subject: [PATCH v3 5/8] pwm: rzg2l-gpt: Add RZ/G3E support Date: Tue, 23 Sep 2025 15:45:09 +0100 Message-ID: <20250923144524.191892-6-biju.das.jz@bp.renesas.com> X-Mailer: git-send-email 2.43.0 In-Reply-To: <20250923144524.191892-1-biju.das.jz@bp.renesas.com> References: <20250923144524.191892-1-biju.das.jz@bp.renesas.com> Precedence: bulk X-Mailing-List: linux-pwm@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 From: Biju Das Add RZ/G3E GPT support. It has multiple clocks and resets compared to RZ/G2L. Also prescale field width and factor for calculating prescale are different. Reviewed-by: Tommaso Merciai Signed-off-by: Biju Das --- v2->v3: * No change. v1->v2: * Added link to hardware manual * Updated limitation section * Collected tag --- drivers/pwm/pwm-rzg2l-gpt.c | 46 +++++++++++++++++++++++++++++++++++-- 1 file changed, 44 insertions(+), 2 deletions(-) diff --git a/drivers/pwm/pwm-rzg2l-gpt.c b/drivers/pwm/pwm-rzg2l-gpt.c index 0af3aaf1917a..087bc3c0778c 100644 --- a/drivers/pwm/pwm-rzg2l-gpt.c +++ b/drivers/pwm/pwm-rzg2l-gpt.c @@ -6,15 +6,21 @@ * * Hardware manual for this IP can be found here * https://www.renesas.com/eu/en/document/mah/rzg2l-group-rzg2lc-group-users-manual-hardware-0?language=en + * https://www.renesas.com/en/document/mah/rzg3e-group-users-manual-hardware * * Limitations: * - Counter must be stopped before modifying Mode and Prescaler. * - When PWM is disabled, the output is driven to inactive. * - While the hardware supports both polarities, the driver (for now) * only handles normal polarity. - * - General PWM Timer (GPT) has 8 HW channels for PWM operations and - * each HW channel have 2 IOs. + * - For RZ/G2L, the General PWM Timer (GPT) has 8 HW channels for PWM + operations and each HW channel have 2 IOs (GTIOCn{A, B}). * - Each IO is modelled as an independent PWM channel. + * - For RZ/G3E, the General PWM Timer (GPT) has 16 HW channels for PWM + operations (GPT0: 8 channels, GPT1: 8 Channels) and each HW channel + have 4 IOs (GTIOCn{A,AN,B,BN}). The 2 extra IOs GTIOCnAN and GTIOCnBN + in RZ/G3E are anti-phase signals of GTIOCnA and GTIOCnB. The + anti-phase signals of RZ/G3E are not modelled as PWM channel. * - When both channels are used, disabling the channel on one stops the * other. * - When both channels are used, the period of both IOs in the HW channel @@ -153,6 +159,27 @@ static u8 rzg2l_gpt_calculate_prescale(u64 period_ticks) return prescale; } +static u8 rzg3e_gpt_calculate_prescale(u64 period_ticks) +{ + u32 prescaled_period_ticks; + u8 prescale; + + prescaled_period_ticks = period_ticks >> 32; + if (prescaled_period_ticks >= 64 && prescaled_period_ticks < 256) { + prescale = 6; + } else if (prescaled_period_ticks >= 256 && prescaled_period_ticks < 1024) { + prescale = 8; + } else if (prescaled_period_ticks >= 1024) { + prescale = 10; + } else { + prescale = fls(prescaled_period_ticks); + if (prescale > 1) + prescale -= 1; + } + + return prescale; +} + static int rzg2l_gpt_request(struct pwm_chip *chip, struct pwm_device *pwm) { struct rzg2l_gpt_chip *rzg2l_gpt = to_rzg2l_gpt_chip(chip); @@ -459,6 +486,14 @@ static int rzg2l_gpt_probe(struct platform_device *pdev) if (IS_ERR(rstc)) return dev_err_probe(dev, PTR_ERR(rstc), "Cannot deassert reset control\n"); + rstc = devm_reset_control_get_optional_exclusive_deasserted(dev, "rst_s"); + if (IS_ERR(rstc)) + return dev_err_probe(dev, PTR_ERR(rstc), "Cannot deassert rst_s reset\n"); + + clk = devm_clk_get_optional_enabled(dev, "bus"); + if (IS_ERR(clk)) + return dev_err_probe(dev, PTR_ERR(clk), "Cannot get bus clock\n"); + clk = devm_clk_get_enabled(dev, NULL); if (IS_ERR(clk)) return dev_err_probe(dev, PTR_ERR(clk), "Cannot get clock\n"); @@ -497,6 +532,12 @@ static int rzg2l_gpt_probe(struct platform_device *pdev) return 0; } +static const struct rzg2l_gpt_info rzg3e_data = { + .calculate_prescale = rzg3e_gpt_calculate_prescale, + .gtcr_tpcs_mask = GENMASK(26, 23), + .prescale_pow_of_two_mult_factor = 1, +}; + static const struct rzg2l_gpt_info rzg2l_data = { .calculate_prescale = rzg2l_gpt_calculate_prescale, .gtcr_tpcs_mask = GENMASK(26, 24), @@ -504,6 +545,7 @@ static const struct rzg2l_gpt_info rzg2l_data = { }; static const struct of_device_id rzg2l_gpt_of_table[] = { + { .compatible = "renesas,r9a09g047-gpt", .data = &rzg3e_data }, { .compatible = "renesas,rzg2l-gpt", .data = &rzg2l_data }, { /* Sentinel */ } };