From patchwork Tue Apr 29 12:51:32 2025 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Fabrice Gasnier X-Patchwork-Id: 2078928 Return-Path: X-Original-To: incoming@patchwork.ozlabs.org Delivered-To: patchwork-incoming@legolas.ozlabs.org Authentication-Results: legolas.ozlabs.org; dkim=pass (2048-bit key; unprotected) header.d=foss.st.com header.i=@foss.st.com header.a=rsa-sha256 header.s=selector1 header.b=klSOr//a; dkim-atps=neutral Authentication-Results: legolas.ozlabs.org; spf=pass (sender SPF authorized) smtp.mailfrom=vger.kernel.org (client-ip=2604:1380:45e3:2400::1; helo=sv.mirrors.kernel.org; envelope-from=linux-pwm+bounces-5763-incoming=patchwork.ozlabs.org@vger.kernel.org; receiver=patchwork.ozlabs.org) Received: from sv.mirrors.kernel.org (sv.mirrors.kernel.org [IPv6:2604:1380:45e3:2400::1]) (using TLSv1.3 with cipher TLS_AES_256_GCM_SHA384 (256/256 bits) key-exchange X25519 server-signature ECDSA (secp384r1) server-digest SHA384) (No client certificate requested) by legolas.ozlabs.org (Postfix) with ESMTPS id 4Zn0fb4q9Jz1yMf for ; Tue, 29 Apr 2025 22:55:35 +1000 (AEST) Received: from smtp.subspace.kernel.org (relay.kernel.org [52.25.139.140]) (using TLSv1.2 with cipher ECDHE-ECDSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by sv.mirrors.kernel.org (Postfix) with ESMTPS id 0ABB8980770 for ; Tue, 29 Apr 2025 12:55:16 +0000 (UTC) Received: from localhost.localdomain (localhost.localdomain [127.0.0.1]) by smtp.subspace.kernel.org (Postfix) with ESMTP id 9AE652D1F63; Tue, 29 Apr 2025 12:55:00 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=foss.st.com header.i=@foss.st.com header.b="klSOr//a" X-Original-To: linux-pwm@vger.kernel.org Received: from mx08-00178001.pphosted.com (mx08-00178001.pphosted.com [91.207.212.93]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id B40EC2C2ABF; Tue, 29 Apr 2025 12:54:58 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=91.207.212.93 ARC-Seal: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1745931300; cv=none; b=lJX65i5WY0Z6biLZANAxMYJDSuQkLuyl2f0UPJ1I6yQr/H3HKW80icXDutrnOWDQE3YbBqhh87hDa4Jt953qwc77nfwE/hLXHKOgkCAmR7XrXNFyYhnsrf60reTTIaDP8fbtdX+emg4XDCHh+t1teI2z4MLj/+apJs4fLoj0S3E= ARC-Message-Signature: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1745931300; c=relaxed/simple; bh=1SGEnF4/9TakbDkU2bjvjWnbZwqNoZ3b+Nm0Y4ux24E=; h=From:To:CC:Subject:Date:Message-ID:In-Reply-To:References: MIME-Version:Content-Type; b=K3VMGunAUwqvBvj/gNRNwCOhlX8/MtLU7iRmVQfGinOIWR46nwCquaqMEtlh6ZjQTCiQ34/iHzk+JLaQxxrHaEbsf/EwlfYU4Nysj0OfYGO2Q7uH/4k1ME1eqd5hba55nE6euxSWA/YEtQzIfgm95fecf6b370J91G+W0QD+D3g= ARC-Authentication-Results: i=1; smtp.subspace.kernel.org; dmarc=pass (p=none dis=none) header.from=foss.st.com; spf=pass smtp.mailfrom=foss.st.com; dkim=pass (2048-bit key) header.d=foss.st.com header.i=@foss.st.com header.b=klSOr//a; arc=none smtp.client-ip=91.207.212.93 Authentication-Results: smtp.subspace.kernel.org; dmarc=pass (p=none dis=none) header.from=foss.st.com Authentication-Results: smtp.subspace.kernel.org; spf=pass smtp.mailfrom=foss.st.com Received: from pps.filterd (m0369457.ppops.net [127.0.0.1]) by mx07-00178001.pphosted.com (8.18.1.2/8.18.1.2) with ESMTP id 53TBEmsK010884; Tue, 29 Apr 2025 14:54:48 +0200 DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=foss.st.com; h= cc:content-transfer-encoding:content-type:date:from:in-reply-to :message-id:mime-version:references:subject:to; s=selector1; bh= Bf4Jif3iTwu6xhT/icuxJcCkmXcEX9OzuYCH60IJsfg=; b=klSOr//ak+Jo4+Wc HpAbR5TH3+oTliLKBCO0UFpYd0Cv/lsNabdrgGOJy4EYAkR7mOxtzJuPP3anp+C8 N/h98ogWlOeyt5gzJMIe+x/i2oqJZgQIB6ba/SaxfUhSJFL0JRUGc6fb9+XJ9+Eb ElVW4AF6erQiJZHYK3j5EsPY5cB8NtQwfwDrkKTQvrvAmfzcCBbsgCXWO2UVWXJ0 UbKkcKKVLPEGIFsJN5dd99Q8+mjeSeSnEg2czpRvzuG4kpWrrtGpdZPLt2LpJUvb 91h2WftSmZxP3gU3kgPDiBxFFTBcMtbVfimBmNXaPQRTzWNCrksN2l+4+ZfyYyEz rvRCoA== Received: from beta.dmz-ap.st.com (beta.dmz-ap.st.com [138.198.100.35]) by mx07-00178001.pphosted.com (PPS) with ESMTPS id 469aengsj6-1 (version=TLSv1.2 cipher=ECDHE-RSA-AES256-GCM-SHA384 bits=256 verify=NOT); Tue, 29 Apr 2025 14:54:48 +0200 (MEST) Received: from euls16034.sgp.st.com (euls16034.sgp.st.com [10.75.44.20]) by beta.dmz-ap.st.com (STMicroelectronics) with ESMTP id 28D3A40081; Tue, 29 Apr 2025 14:53:48 +0200 (CEST) Received: from Webmail-eu.st.com (eqndag1node5.st.com [10.75.129.134]) by euls16034.sgp.st.com (STMicroelectronics) with ESMTP id 1D61FA7FB54; Tue, 29 Apr 2025 14:51:51 +0200 (CEST) Received: from SAFDAG1NODE1.st.com (10.75.90.17) by EQNDAG1NODE5.st.com (10.75.129.134) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_128_GCM_SHA256) id 15.1.2507.39; Tue, 29 Apr 2025 14:51:50 +0200 Received: from localhost (10.252.5.160) by SAFDAG1NODE1.st.com (10.75.90.17) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_128_GCM_SHA256) id 15.1.2507.39; Tue, 29 Apr 2025 14:51:50 +0200 From: Fabrice Gasnier To: , , , CC: , , , , , , , , , , , , , , , Subject: [PATCH v6 6/7] arm64: dts: st: add low-power timer nodes on stm32mp251 Date: Tue, 29 Apr 2025 14:51:32 +0200 Message-ID: <20250429125133.1574167-7-fabrice.gasnier@foss.st.com> X-Mailer: git-send-email 2.25.1 In-Reply-To: <20250429125133.1574167-1-fabrice.gasnier@foss.st.com> References: <20250429125133.1574167-1-fabrice.gasnier@foss.st.com> Precedence: bulk X-Mailing-List: linux-pwm@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 X-ClientProxiedBy: EQNCAS1NODE4.st.com (10.75.129.82) To SAFDAG1NODE1.st.com (10.75.90.17) X-Proofpoint-Virus-Version: vendor=baseguard engine=ICAP:2.0.293,Aquarius:18.0.1099,Hydra:6.0.736,FMLib:17.12.80.40 definitions=2025-04-29_04,2025-04-24_02,2025-02-21_01 Add low-power timer (LPTimer) support on STM32MP25 SoC. The full feature set is implemented in LPTIM1/2/3/4. LPTIM5 supports a smaller set of features (no capture/compare) channel. Still, LPTIM5 can be used as single PWM, counter, trigger or timer. Signed-off-by: Fabrice Gasnier --- Changes in V2: - Adopt two compatibles: newly introduced "st,stm32mp25-..." compatible, and fallback "st,stm32-...". --- arch/arm64/boot/dts/st/stm32mp251.dtsi | 177 +++++++++++++++++++++++++ 1 file changed, 177 insertions(+) diff --git a/arch/arm64/boot/dts/st/stm32mp251.dtsi b/arch/arm64/boot/dts/st/stm32mp251.dtsi index f3c6cdfd7008..505176276e72 100644 --- a/arch/arm64/boot/dts/st/stm32mp251.dtsi +++ b/arch/arm64/boot/dts/st/stm32mp251.dtsi @@ -238,6 +238,78 @@ rifsc: bus@42080000 { #access-controller-cells = <1>; ranges; + lptimer1: timer@40090000 { + compatible = "st,stm32mp25-lptimer", "st,stm32-lptimer"; + reg = <0x40090000 0x400>; + interrupts-extended = <&exti1 47 IRQ_TYPE_LEVEL_HIGH>; + clocks = <&rcc CK_KER_LPTIM1>; + clock-names = "mux"; + #address-cells = <1>; + #size-cells = <0>; + access-controllers = <&rifsc 17>; + power-domains = <&RET_PD>; + wakeup-source; + status = "disabled"; + + counter { + compatible = "st,stm32mp25-lptimer-counter", "st,stm32-lptimer-counter"; + status = "disabled"; + }; + + pwm { + compatible = "st,stm32mp25-pwm-lp", "st,stm32-pwm-lp"; + #pwm-cells = <3>; + status = "disabled"; + }; + + timer { + compatible = "st,stm32mp25-lptimer-timer", "st,stm32-lptimer-timer"; + status = "disabled"; + }; + + trigger@0 { + compatible = "st,stm32mp25-lptimer-trigger", "st,stm32-lptimer-trigger"; + reg = <0>; + status = "disabled"; + }; + }; + + lptimer2: timer@400a0000 { + compatible = "st,stm32mp25-lptimer", "st,stm32-lptimer"; + reg = <0x400a0000 0x400>; + interrupts-extended = <&exti1 48 IRQ_TYPE_LEVEL_HIGH>; + clocks = <&rcc CK_KER_LPTIM2>; + clock-names = "mux"; + #address-cells = <1>; + #size-cells = <0>; + access-controllers = <&rifsc 18>; + power-domains = <&RET_PD>; + wakeup-source; + status = "disabled"; + + counter { + compatible = "st,stm32mp25-lptimer-counter", "st,stm32-lptimer-counter"; + status = "disabled"; + }; + + pwm { + compatible = "st,stm32mp25-pwm-lp", "st,stm32-pwm-lp"; + #pwm-cells = <3>; + status = "disabled"; + }; + + timer { + compatible = "st,stm32mp25-lptimer-timer", "st,stm32-lptimer-timer"; + status = "disabled"; + }; + + trigger@1 { + compatible = "st,stm32mp25-lptimer-trigger", "st,stm32-lptimer-trigger"; + reg = <1>; + status = "disabled"; + }; + }; + i2s2: audio-controller@400b0000 { compatible = "st,stm32mp25-i2s"; reg = <0x400b0000 0x400>; @@ -799,6 +871,111 @@ i2c8: i2c@46040000 { status = "disabled"; }; + lptimer3: timer@46050000 { + compatible = "st,stm32mp25-lptimer", "st,stm32-lptimer"; + reg = <0x46050000 0x400>; + interrupts-extended = <&exti2 29 IRQ_TYPE_LEVEL_HIGH>; + clocks = <&rcc CK_KER_LPTIM3>; + clock-names = "mux"; + #address-cells = <1>; + #size-cells = <0>; + access-controllers = <&rifsc 19>; + wakeup-source; + status = "disabled"; + + counter { + compatible = "st,stm32mp25-lptimer-counter", "st,stm32-lptimer-counter"; + status = "disabled"; + }; + + pwm { + compatible = "st,stm32mp25-pwm-lp", "st,stm32-pwm-lp"; + #pwm-cells = <3>; + status = "disabled"; + }; + + timer { + compatible = "st,stm32mp25-lptimer-timer", "st,stm32-lptimer-timer"; + status = "disabled"; + }; + + trigger@2 { + compatible = "st,stm32mp25-lptimer-trigger", "st,stm32-lptimer-trigger"; + reg = <2>; + status = "disabled"; + }; + }; + + lptimer4: timer@46060000 { + compatible = "st,stm32mp25-lptimer", "st,stm32-lptimer"; + reg = <0x46060000 0x400>; + interrupts-extended = <&exti2 30 IRQ_TYPE_LEVEL_HIGH>; + clocks = <&rcc CK_KER_LPTIM4>; + clock-names = "mux"; + #address-cells = <1>; + #size-cells = <0>; + access-controllers = <&rifsc 20>; + wakeup-source; + status = "disabled"; + + counter { + compatible = "st,stm32mp25-lptimer-counter", "st,stm32-lptimer-counter"; + status = "disabled"; + }; + + pwm { + compatible = "st,stm32mp25-pwm-lp", "st,stm32-pwm-lp"; + #pwm-cells = <3>; + status = "disabled"; + }; + + timer { + compatible = "st,stm32mp25-lptimer-timer", "st,stm32-lptimer-timer"; + status = "disabled"; + }; + + trigger@3 { + compatible = "st,stm32mp25-lptimer-trigger", "st,stm32-lptimer-trigger"; + reg = <3>; + status = "disabled"; + }; + }; + + lptimer5: timer@46070000 { + compatible = "st,stm32mp25-lptimer", "st,stm32-lptimer"; + reg = <0x46070000 0x400>; + interrupts-extended = <&exti2 31 IRQ_TYPE_LEVEL_HIGH>; + clocks = <&rcc CK_KER_LPTIM5>; + clock-names = "mux"; + #address-cells = <1>; + #size-cells = <0>; + access-controllers = <&rifsc 21>; + wakeup-source; + status = "disabled"; + + counter { + compatible = "st,stm32mp25-lptimer-counter", "st,stm32-lptimer-counter"; + status = "disabled"; + }; + + pwm { + compatible = "st,stm32mp25-pwm-lp", "st,stm32-pwm-lp"; + #pwm-cells = <3>; + status = "disabled"; + }; + + timer { + compatible = "st,stm32mp25-lptimer-timer", "st,stm32-lptimer-timer"; + status = "disabled"; + }; + + trigger@4 { + compatible = "st,stm32mp25-lptimer-trigger", "st,stm32-lptimer-trigger"; + reg = <4>; + status = "disabled"; + }; + }; + csi: csi@48020000 { compatible = "st,stm32mp25-csi"; reg = <0x48020000 0x2000>;