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Mon, 23 Oct 2023 07:41:17 -0700 (PDT) From: Alexandre Mergnat Date: Mon, 23 Oct 2023 16:40:17 +0200 Subject: [PATCH 17/18] arm64: dts: mediatek: add display blocks support for the MT8365 SoC MIME-Version: 1.0 Message-Id: <20231023-display-support-v1-17-5c860ed5c33b@baylibre.com> References: <20231023-display-support-v1-0-5c860ed5c33b@baylibre.com> In-Reply-To: <20231023-display-support-v1-0-5c860ed5c33b@baylibre.com> To: Chun-Kuang Hu , Philipp Zabel , David Airlie , Daniel Vetter , Rob Herring , Krzysztof Kozlowski , Conor Dooley , Matthias Brugger , AngeloGioacchino Del Regno , Jitao Shi , Xinlei Lee , CK Hu , Thierry Reding , =?utf-8?q?Uwe_Kleine-K=C3=B6nig?= , Catalin Marinas , Will Deacon Cc: dri-devel@lists.freedesktop.org, linux-mediatek@lists.infradead.org, devicetree@vger.kernel.org, linux-kernel@vger.kernel.org, linux-arm-kernel@lists.infradead.org, linux-pwm@vger.kernel.org, Alexandre Mergnat X-Mailer: b4 0.12.2 X-Developer-Signature: v=1; a=openpgp-sha256; l=7082; i=amergnat@baylibre.com; h=from:subject:message-id; bh=GrqIHwd0l9+44q9ggVwPid+Zd2sZPQpFOwpuTf1SwWY=; b=owEBbQKS/ZANAwAKAStGSZ1+MdRFAcsmYgBlNoXPPcsd/oUE0a9NY68W+0Ky2eNYAfmRaFOVUlwY Fr2tBLWJAjMEAAEKAB0WIQQjG17X8+qqcA5g/osrRkmdfjHURQUCZTaFzwAKCRArRkmdfjHURVuAD/ 9o/qWcsErVbAO5/ec3rAt7R2x0P+I5D9RaBuukKd7b5m0IE8U2CBqbNivJTaA/t1LbRzwHzC/ah3SS qcyz6vE38fXyjCrpFRt42IuTSxMk4lIIuK4BsyGjPznAyL/HH+70O88uzw4B83x9VvvjFAVjB5YVMt SAwZL+wQ0bI0FnauDW3PCkEqasdIzWz3BRGIolJ7iKRM7iZwkqPdgE9FHCNYIyQvdn+fnFG6ZEDHUA fyJs0SK2JzrQugPsFxjQsQawuQRMPm+/WME13iCojHuImZbJCQIeLyhem98xq7c0ludW+1oMLfifTK y5h+azpqOFnG4PAV2bZN2ECUI/tRB4BQxsCIk3gPprDxOFnDGe7A1F9ubDPtJJijvDMF1P+kiLHFEU RMPk8O/Y3/c2bV7RzKBjy00byPbBTAuXzn1AQZBEf5OtXaRs7wBoe/RzeUUAU2zOzy3wimMs60FYmy DKhDKnjDBkS9199Ia+X3b4UeW1l6EhCWGSmovYgyBiR6sG3/H6l5TK93YAKRw0SQH9gsdZHHwJ9iE2 Dwza+H2EfJkCqNLCWo4QEyZ3kq9oK0VipWezsJM97k7wcb4wwC9QyPoN5P0uQdPvIJoaNvdibfJTjC CtBA02Hj+qRBmGlS6x6KvQfcGrgNZn3l/9H00K1MIdGTlw1bgYX4tfEJKang== X-Developer-Key: i=amergnat@baylibre.com; a=openpgp; fpr=231B5ED7F3EAAA700E60FE8B2B46499D7E31D445 X-Spam-Status: No, score=-1.9 required=5.0 tests=BAYES_00,DKIM_SIGNED, DKIM_VALID,RCVD_IN_DNSWL_NONE,SPF_HELO_NONE,SPF_PASS autolearn=unavailable autolearn_force=no version=3.4.6 X-Spam-Checker-Version: SpamAssassin 3.4.6 (2021-04-09) on lindbergh.monkeyblade.net Precedence: bulk List-ID: X-Mailing-List: linux-pwm@vger.kernel.org - Add aliases for each display components to help display drivers. - Add the Display Pulse Width Modulation (DISP_PWM) to provide PWM signals for the LED driver of mobile LCM. - Add the MIPI Display Serial Interface (DSI) PHY support. (up to 4-lane output) - Add the display mutex support. - Add the following display component support: - OVL0 (Overlay) - RDMA0 (Data Path Read DMA) - Color0 - CCorr0 (Color Correction) - AAL0 (Adaptive Ambient Light) - GAMMA0 - Dither0 - DSI0 (Display Serial Interface) - RDMA1 (Data Path Read DMA) - DPI0 (Display Parallel Interface) Signed-off-by: Alexandre Mergnat --- arch/arm64/boot/dts/mediatek/mt8365.dtsi | 146 +++++++++++++++++++++++++++++++ 1 file changed, 146 insertions(+) diff --git a/arch/arm64/boot/dts/mediatek/mt8365.dtsi b/arch/arm64/boot/dts/mediatek/mt8365.dtsi index 24581f7410aa..6096358f7d07 100644 --- a/arch/arm64/boot/dts/mediatek/mt8365.dtsi +++ b/arch/arm64/boot/dts/mediatek/mt8365.dtsi @@ -8,6 +8,7 @@ #include #include #include +#include #include #include @@ -17,6 +18,19 @@ / { #address-cells = <2>; #size-cells = <2>; + aliases { + aal0 = &aal0; + ccorr0 = &ccorr0; + color0 = &color0; + dither0 = &dither0; + dpi0 = &dpi0; + dsi0 = &dsi0; + gamma0 = &gamma0; + ovl0 = &ovl0; + rdma0 = &rdma0; + rdma1 = &rdma1; + }; + cpus { #address-cells = <1>; #size-cells = <0>; @@ -607,6 +621,17 @@ spi: spi@1100a000 { status = "disabled"; }; + disp_pwm: pwm@1100e000 { + compatible = "mediatek,mt8365-disp-pwm", + "mediatek,mt8183-disp-pwm"; + reg = <0 0x1100e000 0 0x1000>; + clock-names = "main", "mm"; + clocks = <&topckgen CLK_TOP_DISP_PWM_SEL>, + <&infracfg CLK_IFR_DISP_PWM>; + power-domains = <&spm MT8365_POWER_DOMAIN_MM>; + #pwm-cells = <2>; + }; + i2c3: i2c@1100f000 { compatible = "mediatek,mt8365-i2c", "mediatek,mt8168-i2c"; reg = <0 0x1100f000 0 0xa0>, <0 0x11000200 0 0x80>; @@ -703,6 +728,15 @@ ethernet: ethernet@112a0000 { status = "disabled"; }; + mipi_tx0: dsi-phy@11c00000 { + compatible = "mediatek,mt8365-mipi-tx", "mediatek,mt8183-mipi-tx"; + reg = <0 0x11c00000 0 0x800>; + clock-output-names = "mipi_tx0_pll"; + clocks = <&clk26m>; + #clock-cells = <0>; + #phy-cells = <0>; + }; + u3phy: t-phy@11cc0000 { compatible = "mediatek,mt8365-tphy", "mediatek,generic-tphy-v2"; #address-cells = <1>; @@ -732,6 +766,13 @@ mmsys: syscon@14000000 { #clock-cells = <1>; }; + mutex: mutex@14001000 { + compatible = "mediatek,mt8365-disp-mutex"; + reg = <0 0x14001000 0 0x1000>; + interrupts = ; + power-domains = <&spm MT8365_POWER_DOMAIN_MM>; + }; + smi_common: smi@14002000 { compatible = "mediatek,mt8365-smi-common"; reg = <0 0x14002000 0 0x1000>; @@ -755,6 +796,111 @@ larb0: larb@14003000 { mediatek,larb-id = <0>; }; + ovl0: ovl@1400b000 { + compatible = "mediatek,mt8365-disp-ovl", + "mediatek,mt8192-disp-ovl"; + reg = <0 0x1400b000 0 0x1000>; + clocks = <&mmsys CLK_MM_MM_DISP_OVL0>; + interrupts = ; + iommus = <&iommu M4U_PORT_DISP_OVL0>; + power-domains = <&spm MT8365_POWER_DOMAIN_MM>; + }; + + rdma0: rdma@1400d000 { + compatible = "mediatek,mt8365-disp-rdma", + "mediatek,mt8183-disp-rdma"; + reg = <0 0x1400d000 0 0x1000>; + clocks = <&mmsys CLK_MM_MM_DISP_RDMA0>; + interrupts = ; + iommus = <&iommu M4U_PORT_DISP_RDMA0>; + mediatek,rdma-fifo-size = <5120>; + power-domains = <&spm MT8365_POWER_DOMAIN_MM>; + }; + + color0: color@1400f000 { + compatible = "mediatek,mt8365-disp-color", + "mediatek,mt8173-disp-color"; + reg = <0 0x1400f000 0 0x1000>; + clocks = <&mmsys CLK_MM_MM_DISP_COLOR0>; + interrupts = ; + power-domains = <&spm MT8365_POWER_DOMAIN_MM>; + }; + + ccorr0: ccorr@14010000 { + compatible = "mediatek,mt8365-disp-ccorr", + "mediatek,mt8183-disp-ccorr"; + reg = <0 0x14010000 0 0x1000>; + clocks = <&mmsys CLK_MM_MM_DISP_CCORR0>; + interrupts = ; + power-domains = <&spm MT8365_POWER_DOMAIN_MM>; + }; + + aal0: aal@14011000 { + compatible = "mediatek,mt8365-disp-aal", + "mediatek,mt8183-disp-aal"; + reg = <0 0x14011000 0 0x1000>; + clocks = <&mmsys CLK_MM_MM_DISP_AAL0>; + interrupts = ; + power-domains = <&spm MT8365_POWER_DOMAIN_MM>; + }; + + gamma0: gamma@14012000 { + compatible = "mediatek,mt8365-disp-gamma", + "mediatek,mt8183-disp-gamma"; + reg = <0 0x14012000 0 0x1000>; + clocks = <&mmsys CLK_MM_MM_DISP_GAMMA0>; + interrupts = ; + power-domains = <&spm MT8365_POWER_DOMAIN_MM>; + }; + + dither0: dither@14013000 { + compatible = "mediatek,mt8365-disp-dither", + "mediatek,mt8183-disp-dither"; + reg = <0 0x14013000 0 0x1000>; + clocks = <&mmsys CLK_MM_MM_DISP_DITHER0>; + interrupts = ; + power-domains = <&spm MT8365_POWER_DOMAIN_MM>; + }; + + dsi0: dsi@14014000 { + compatible = "mediatek,mt8183-dsi"; + reg = <0 0x14014000 0 0x1000>; + clock-names = "engine", "digital", "hs"; + clocks = <&mmsys CLK_MM_MM_DSI0>, + <&mmsys CLK_MM_DSI0_DIG_DSI>, + <&mipi_tx0>; + interrupts = ; + phy-names = "dphy"; + phys = <&mipi_tx0>; + power-domains = <&spm MT8365_POWER_DOMAIN_MM>; + }; + + rdma1: rdma@14016000 { + compatible = "mediatek,mt8365-disp-rdma", + "mediatek,mt8183-disp-rdma"; + reg = <0 0x14016000 0 0x1000>; + clocks = <&mmsys CLK_MM_MM_DISP_RDMA1>; + interrupts = ; + iommus = <&iommu M4U_PORT_DISP_RDMA1>; + mediatek,rdma-fifo-size = <2048>; + power-domains = <&spm MT8365_POWER_DOMAIN_MM>; + }; + + dpi0: dpi@14018000 { + compatible = "mediatek,mt8365-dpi"; + reg = <0 0x14018000 0 0x1000>; + assigned-clock-parents = <&topckgen CLK_TOP_LVDSPLL_D4>; + assigned-clocks = <&topckgen CLK_TOP_DPI0_SEL>; + clock-names = "pixel", "engine", "pll", "dpi"; + clocks = <&topckgen CLK_TOP_DPI0_SEL>, + <&mmsys CLK_MM_MM_DPI0>, + <&apmixedsys CLK_APMIXED_LVDSPLL>, + <&mmsys CLK_MM_DPI0_DPI0>; + interrupts = ; + power-domains = <&spm MT8365_POWER_DOMAIN_MM>; + status = "disabled"; + }; + camsys: syscon@15000000 { compatible = "mediatek,mt8365-imgsys", "syscon"; reg = <0 0x15000000 0 0x1000>;