| Message ID | 20221108142226.63161-7-andriy.shevchenko@linux.intel.com |
|---|---|
| State | Superseded |
| Headers | show |
| Series | pinctrl: intel: Enable PWM optional feature | expand |
On Tue, Nov 8, 2022 at 3:22 PM Andy Shevchenko <andriy.shevchenko@linux.intel.com> wrote: > Some of the Communities may have PWM capability. In such cases, > enumerate PWM device via respective driver. User is still responsible > for setting correct pin muxing for the line that needs to output the > signal. > > Signed-off-by: Andy Shevchenko <andriy.shevchenko@linux.intel.com> > Reviewed-by: Mika Westerberg <mika.westerberg@linux.intel.com> So: > +#include <linux/platform_data/x86/pwm-lpss.h> (...) > +static int intel_pinctrl_probe_pwm(struct intel_pinctrl *pctrl, > + struct intel_community *community) > +{ > + static const struct pwm_lpss_boardinfo info = { > + .clk_rate = 19200000, > + .npwm = 1, > + .base_unit_bits = 22, > + .bypass = true, > + }; > + struct pwm_lpss_chip *pwm; > + > + if (!(community->features & PINCTRL_FEATURE_PWM)) > + return 0; > + > + pwm = pwm_lpss_probe(pctrl->dev, community->regs + PWMC, &info); > + if (IS_ERR(pwm) && PTR_ERR(pwm) != -ENODEV) > + return PTR_ERR(pwm); This is alike a boardfile embedded into the pin control driver. It's a bit backwards since we usually go the other direction, i.e. probe a PWM driver or whatever and then that driver request its resources that are assigned from e.g. DT or ACPI, and in this case that would mean it request its pin control handle and the pins get set up. I guess I can be convinced that this hack is the lesser evil :D What is it in the platform that makes this kind of hacks necessary? Inconsistent description in ACPI or is the PWM device simply missing from the DSDT (or whatever is the right form in ACPI) in already shipped devices that need it? Or is it simply impossible to describe the PWM device in ACPI? Yours, Linus Walleij
On Wed, Nov 09, 2022 at 10:08:51AM +0100, Linus Walleij wrote: > On Tue, Nov 8, 2022 at 3:22 PM Andy Shevchenko > <andriy.shevchenko@linux.intel.com> wrote: ... > > + static const struct pwm_lpss_boardinfo info = { > > + .clk_rate = 19200000, > > + .npwm = 1, > > + .base_unit_bits = 22, > > + .bypass = true, > > + }; > > + struct pwm_lpss_chip *pwm; > > + > > + if (!(community->features & PINCTRL_FEATURE_PWM)) > > + return 0; > > + > > + pwm = pwm_lpss_probe(pctrl->dev, community->regs + PWMC, &info); > > + if (IS_ERR(pwm) && PTR_ERR(pwm) != -ENODEV) > > + return PTR_ERR(pwm); > > This is alike a boardfile embedded into the pin control driver. Correct. > It's a bit backwards since we usually go the other direction, i.e. probe > a PWM driver or whatever and then that driver request its resources > that are assigned from e.g. DT or ACPI, and in this case that would > mean it request its pin control handle and the pins get set up. > > I guess I can be convinced that this hack is the lesser evil :D > > What is it in the platform that makes this kind of hacks necessary? The PWM capability is discoverable by the looking for it in the pin control IP MMIO, it's not a separate device, but a sibling (child?) of the pin control, that's not a separate entity. Moreover, not every pin control _community_ has that capability (capabilities are on the Community level and depends on ACPI representation of the communities themself - single device or device per community - the PWM may or may not be easily attached. What you are proposing is to invent at least two additional properties or so for the pin control device description and then to support old platforms, create a board file somewhere else, which will go through all pin control devices, checks the capabilities, then embeds the properties via properties (Either embedded into DSDT, if done in BIOS, or swnodes). Do I get you right? If so, in my opinion it's way more ugly and overkill that the current approach. > Inconsistent description in ACPI or is the PWM device simply > missing from the DSDT (or whatever is the right form in ACPI) > in already shipped devices that need it? Right. > Or is it simply impossible to describe the PWM device in ACPI? It's a dynamic feature and existing firmwares are carved in stone. It might be possible to move the above mentioned uglification to the BIOS. But the horizon of that is 5+ years in case I am able to convince program managers for it (TBH, I don't believe it's feasible, since "Windows works!" mantra, they are not engineers). That said, I agree that this looks not nice, but that's all what Mika and me can come up with to make all this as little ugly and intrusive as possible.
On Wed, Nov 9, 2022 at 10:56 AM Andy Shevchenko <andriy.shevchenko@linux.intel.com> wrote: > On Wed, Nov 09, 2022 at 10:08:51AM +0100, Linus Walleij wrote: > > I guess I can be convinced that this hack is the lesser evil :D > > > > What is it in the platform that makes this kind of hacks necessary? > > The PWM capability is discoverable by the looking for it in the pin > control IP MMIO, it's not a separate device, but a sibling (child?) > of the pin control, that's not a separate entity. OK I get it. > Moreover, not every pin control _community_ has that capability (capabilities > are on the Community level and depends on ACPI representation of the > communities themself - single device or device per community - the PWM may or > may not be easily attached. OK I think I understand it a bit, if ACPI thinks about the PWM as "some feature of the community" then that is how it is, we have this bad fit between device tree and Linux internals at times as well, then spawning a device from another one is the way to go, we need to consider the option that it is Linux that is weird at times, not the HW description. > What you are proposing is to invent at least two additional properties or so > for the pin control device description and then to support old platforms, > create a board file somewhere else, which will go through all pin control > devices, checks the capabilities, then embeds the properties via properties > (Either embedded into DSDT, if done in BIOS, or swnodes). > > Do I get you right? > > If so, in my opinion it's way more ugly and overkill that the current > approach. No I just wanted to understand things better. This small hack in the pin controller is way better than a bigger and widespread hack somewhere else. > That said, I agree that this looks not nice, but that's all what > Mika and me can come up with to make all this as little ugly and > intrusive as possible. I can live with it, rough consensus and running code. Acked-by: Linus Walleij <linus.walleij@linaro.org> Yours, Linus Walleij
On Wed, Nov 09, 2022 at 11:08:04AM +0100, Linus Walleij wrote: > On Wed, Nov 9, 2022 at 10:56 AM Andy Shevchenko > <andriy.shevchenko@linux.intel.com> wrote: > > On Wed, Nov 09, 2022 at 10:08:51AM +0100, Linus Walleij wrote: ... > > > I guess I can be convinced that this hack is the lesser evil :D > > > > > > What is it in the platform that makes this kind of hacks necessary? > > > > The PWM capability is discoverable by the looking for it in the pin > > control IP MMIO, it's not a separate device, but a sibling (child?) > > of the pin control, that's not a separate entity. > > OK I get it. > > > Moreover, not every pin control _community_ has that capability (capabilities > > are on the Community level and depends on ACPI representation of the > > communities themself - single device or device per community - the PWM may or > > may not be easily attached. > > OK I think I understand it a bit, if ACPI thinks about the PWM > as "some feature of the community" then that is how it is, we have > this bad fit between device tree and Linux internals at times as well, > then spawning a device from another one is the way to go, we need > to consider the option that it is Linux that is weird at times, not the > HW description. The problem here is not the impossibility to do the things. The problem is that things are done and validated on a Windows system. After that it close to impossible to update the firmware or perform any architectural changes. OTOH, announcing the separate device out of the existing MMIO space doesn't sound right from the software point of view that should follow the hardware representation. Ideally, this should be an adaptive MFD-like device, but it makes things even more complicated than has been discussed already. (Note, that some of the pin control drivers are enumerated as platform devices, and that code should also be taken into account) ... > > That said, I agree that this looks not nice, but that's all what > > Mika and me can come up with to make all this as little ugly and > > intrusive as possible. > > I can live with it, rough consensus and running code. > Acked-by: Linus Walleij <linus.walleij@linaro.org> Thank you!
On Tue, Nov 08, 2022 at 04:22:26PM +0200, Andy Shevchenko wrote: > Some of the Communities may have PWM capability. In such cases, > enumerate PWM device via respective driver. User is still responsible > for setting correct pin muxing for the line that needs to output the > signal. > > Signed-off-by: Andy Shevchenko <andriy.shevchenko@linux.intel.com> > Reviewed-by: Mika Westerberg <mika.westerberg@linux.intel.com> > --- > drivers/pinctrl/intel/pinctrl-intel.c | 29 +++++++++++++++++++++++++++ > 1 file changed, 29 insertions(+) > > diff --git a/drivers/pinctrl/intel/pinctrl-intel.c b/drivers/pinctrl/intel/pinctrl-intel.c > index 6e630e87fed6..6b685ff7041f 100644 > --- a/drivers/pinctrl/intel/pinctrl-intel.c > +++ b/drivers/pinctrl/intel/pinctrl-intel.c > @@ -24,6 +24,8 @@ > #include <linux/pinctrl/pinctrl.h> > #include <linux/pinctrl/pinmux.h> > > +#include <linux/platform_data/x86/pwm-lpss.h> > + > #include "../core.h" > #include "pinctrl-intel.h" > > @@ -49,6 +51,8 @@ > #define PADOWN_MASK(p) (GENMASK(3, 0) << PADOWN_SHIFT(p)) > #define PADOWN_GPP(p) ((p) / 8) > > +#define PWMC 0x204 > + > /* Offset from pad_regs */ > #define PADCFG0 0x000 > #define PADCFG0_RXEVCFG_SHIFT 25 > @@ -1502,6 +1506,27 @@ static int intel_pinctrl_pm_init(struct intel_pinctrl *pctrl) > return 0; > } > > +static int intel_pinctrl_probe_pwm(struct intel_pinctrl *pctrl, > + struct intel_community *community) > +{ > + static const struct pwm_lpss_boardinfo info = { > + .clk_rate = 19200000, > + .npwm = 1, > + .base_unit_bits = 22, > + .bypass = true, > + }; > + struct pwm_lpss_chip *pwm; > + > + if (!(community->features & PINCTRL_FEATURE_PWM)) > + return 0; > + > + pwm = pwm_lpss_probe(pctrl->dev, community->regs + PWMC, &info); > + if (IS_ERR(pwm) && PTR_ERR(pwm) != -ENODEV) > + return PTR_ERR(pwm); Linus and Andy already agreed that this patch is ugly. I wonder if this here would be a bit less ugly if you do: if (IS_REACHABLE(...)) { pwm = pwm_lpss_probe(...); ... } and drop the check PTR_ERR(pwm) != -ENODEV (which might have a different semantic than "the pwm driver isn't available"). Best regards Uwe
On Thu, Nov 10, 2022 at 9:45 AM Uwe Kleine-König <u.kleine-koenig@pengutronix.de> wrote: > On Tue, Nov 08, 2022 at 04:22:26PM +0200, Andy Shevchenko wrote: > > Some of the Communities may have PWM capability. In such cases, > > enumerate PWM device via respective driver. User is still responsible > > for setting correct pin muxing for the line that needs to output the > > signal. ... > > + pwm = pwm_lpss_probe(pctrl->dev, community->regs + PWMC, &info); > > + if (IS_ERR(pwm) && PTR_ERR(pwm) != -ENODEV) > > + return PTR_ERR(pwm); > > Linus and Andy already agreed that this patch is ugly. I wonder if this > here would be a bit less ugly if you do: > > if (IS_REACHABLE(...)) { > pwm = pwm_lpss_probe(...); > ... > > > } > > and drop the check PTR_ERR(pwm) != -ENODEV (which might have a different > semantic than "the pwm driver isn't available"). I will think about it (in such case the comment against the previous patch makes more sense to me). Thank you for the review!
diff --git a/drivers/pinctrl/intel/pinctrl-intel.c b/drivers/pinctrl/intel/pinctrl-intel.c index 6e630e87fed6..6b685ff7041f 100644 --- a/drivers/pinctrl/intel/pinctrl-intel.c +++ b/drivers/pinctrl/intel/pinctrl-intel.c @@ -24,6 +24,8 @@ #include <linux/pinctrl/pinctrl.h> #include <linux/pinctrl/pinmux.h> +#include <linux/platform_data/x86/pwm-lpss.h> + #include "../core.h" #include "pinctrl-intel.h" @@ -49,6 +51,8 @@ #define PADOWN_MASK(p) (GENMASK(3, 0) << PADOWN_SHIFT(p)) #define PADOWN_GPP(p) ((p) / 8) +#define PWMC 0x204 + /* Offset from pad_regs */ #define PADCFG0 0x000 #define PADCFG0_RXEVCFG_SHIFT 25 @@ -1502,6 +1506,27 @@ static int intel_pinctrl_pm_init(struct intel_pinctrl *pctrl) return 0; } +static int intel_pinctrl_probe_pwm(struct intel_pinctrl *pctrl, + struct intel_community *community) +{ + static const struct pwm_lpss_boardinfo info = { + .clk_rate = 19200000, + .npwm = 1, + .base_unit_bits = 22, + .bypass = true, + }; + struct pwm_lpss_chip *pwm; + + if (!(community->features & PINCTRL_FEATURE_PWM)) + return 0; + + pwm = pwm_lpss_probe(pctrl->dev, community->regs + PWMC, &info); + if (IS_ERR(pwm) && PTR_ERR(pwm) != -ENODEV) + return PTR_ERR(pwm); + + return 0; +} + static int intel_pinctrl_probe(struct platform_device *pdev, const struct intel_pinctrl_soc_data *soc_data) { @@ -1588,6 +1613,10 @@ static int intel_pinctrl_probe(struct platform_device *pdev, ret = intel_pinctrl_add_padgroups_by_size(pctrl, community); if (ret) return ret; + + ret = intel_pinctrl_probe_pwm(pctrl, community); + if (ret) + return ret; } irq = platform_get_irq(pdev, 0);