Message ID | 20220510151112.16249-8-biju.das.jz@bp.renesas.com |
---|---|
State | Handled Elsewhere |
Headers | show |
Series | Add RZ/G2L POEG support | expand |
diff --git a/arch/arm64/boot/dts/renesas/rzg2l-smarc.dtsi b/arch/arm64/boot/dts/renesas/rzg2l-smarc.dtsi index 8fb68e95f1d7..f1fb9cecc49b 100644 --- a/arch/arm64/boot/dts/renesas/rzg2l-smarc.dtsi +++ b/arch/arm64/boot/dts/renesas/rzg2l-smarc.dtsi @@ -42,6 +42,22 @@ wm8978: codec@1a { }; }; +&poegga { + status = "okay"; +}; + +&poeggb { + status = "okay"; +}; + +&poeggc { + status = "okay"; +}; + +&poeggd { + status = "okay"; +}; + /* * To enable SCIF2 (SER0) on PMOD1 (CN7) * SW1 should be at position 2->3 so that SER0_CTS# line is activated
Enable POEGG{A,B,C,D} on RZ/{G2,V2}L SMARC EVK. Signed-off-by: Biju Das <biju.das.jz@bp.renesas.com> --- arch/arm64/boot/dts/renesas/rzg2l-smarc.dtsi | 16 ++++++++++++++++ 1 file changed, 16 insertions(+)