From patchwork Sun Aug 8 13:24:31 2021 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Jitao Shi X-Patchwork-Id: 1514798 Return-Path: X-Original-To: incoming@patchwork.ozlabs.org Delivered-To: patchwork-incoming@bilbo.ozlabs.org Authentication-Results: ozlabs.org; spf=pass (sender SPF authorized) smtp.mailfrom=vger.kernel.org (client-ip=23.128.96.18; helo=vger.kernel.org; envelope-from=linux-pwm-owner@vger.kernel.org; receiver=) Authentication-Results: ozlabs.org; dkim=pass (1024-bit key; unprotected) header.d=mediatek.com header.i=@mediatek.com header.a=rsa-sha256 header.s=dk header.b=PPXy9IVT; dkim-atps=neutral Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by ozlabs.org (Postfix) with ESMTP id 4GjKhX2Qw3z9s5R for ; Sun, 8 Aug 2021 23:25:16 +1000 (AEST) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S231467AbhHHNZR (ORCPT ); Sun, 8 Aug 2021 09:25:17 -0400 Received: from mailgw02.mediatek.com ([1.203.163.81]:39830 "EHLO mailgw02.mediatek.com" rhost-flags-OK-FAIL-OK-FAIL) by vger.kernel.org with ESMTP id S231401AbhHHNZI (ORCPT ); Sun, 8 Aug 2021 09:25:08 -0400 X-UUID: 84c074e6b30140acaf9b620bb3b3900c-20210808 DKIM-Signature: v=1; a=rsa-sha256; q=dns/txt; c=relaxed/relaxed; d=mediatek.com; s=dk; h=Content-Transfer-Encoding:Content-Type:MIME-Version:References:In-Reply-To:Message-ID:Date:Subject:CC:To:From; bh=tM+NAWWNnNhPu8Jhbb2yxWWm9Io9X8Hw5AFm5lz7rYk=; b=PPXy9IVToI1JLtX+fmX9lNznFnRbFHEvdVeax7HJaUe8uiTi3zskHFBgapMz3wJ9hSc5SLSzEISv3ABF/8JT/cMocCKjUp2plrHNT96W3JV1+PIVHc0B5C6nGRf8hWJa97jvyJ3iSoEPIXIBps+H62KLjP3cSV+gDAM+XrEYmxo=; X-UUID: 84c074e6b30140acaf9b620bb3b3900c-20210808 Received: from mtkcas35.mediatek.inc [(172.27.4.253)] by mailgw02.mediatek.com (envelope-from ) (mailgw01.mediatek.com ESMTP with TLSv1.2 ECDHE-RSA-AES256-SHA384 256/256) with ESMTP id 1295779064; Sun, 08 Aug 2021 21:24:44 +0800 Received: from MTKCAS36.mediatek.inc (172.27.4.186) by MTKMBS33N2.mediatek.inc (172.27.4.76) with Microsoft SMTP Server (TLS) id 15.0.1497.2; Sun, 8 Aug 2021 21:24:39 +0800 Received: from mszsdclx1018.gcn.mediatek.inc (10.16.6.18) by MTKCAS36.mediatek.inc (172.27.4.170) with Microsoft SMTP Server id 15.0.1497.2 via Frontend Transport; Sun, 8 Aug 2021 21:24:38 +0800 From: Jitao Shi To: Thierry Reding , Lee Jones , =?utf-8?q?Uwe_Kleine-K=C3=B6nig?= , Matthias Brugger CC: , , , , , , , , , , , Jitao Shi Subject: [PATCH v7 3/5] pwm: mtk_disp: implement atomic API .apply() Date: Sun, 8 Aug 2021 21:24:31 +0800 Message-ID: <20210808132433.66037-4-jitao.shi@mediatek.com> X-Mailer: git-send-email 2.25.1 In-Reply-To: <20210808132433.66037-1-jitao.shi@mediatek.com> References: <20210808132433.66037-1-jitao.shi@mediatek.com> MIME-Version: 1.0 X-TM-SNTS-SMTP: 4DAA6490F08629866DF748D93C252BA27607E40579FF54F1C8D7E55B7CD856012000:8 X-MTK: N Precedence: bulk List-ID: X-Mailing-List: linux-pwm@vger.kernel.org Switch the driver to support the .apply() method. Signed-off-by: Jitao Shi --- drivers/pwm/pwm-mtk-disp.c | 93 ++++++++++++++++---------------------- 1 file changed, 38 insertions(+), 55 deletions(-) diff --git a/drivers/pwm/pwm-mtk-disp.c b/drivers/pwm/pwm-mtk-disp.c index 1070d78d4940..599d7dd8ecab 100644 --- a/drivers/pwm/pwm-mtk-disp.c +++ b/drivers/pwm/pwm-mtk-disp.c @@ -47,6 +47,7 @@ struct mtk_disp_pwm { struct clk *clk_main; struct clk *clk_mm; void __iomem *base; + bool enabled; }; static inline struct mtk_disp_pwm *to_mtk_disp_pwm(struct pwm_chip *chip) @@ -66,25 +67,42 @@ static void mtk_disp_pwm_update_bits(struct mtk_disp_pwm *mdp, u32 offset, writel(value, address); } -static int mtk_disp_pwm_config(struct pwm_chip *chip, struct pwm_device *pwm, - int duty_ns, int period_ns) +static int mtk_disp_pwm_apply(struct pwm_chip *chip, struct pwm_device *pwm, + const struct pwm_state *state) { struct mtk_disp_pwm *mdp = to_mtk_disp_pwm(chip); u32 clk_div, period, high_width, value; u64 div, rate; int err; - err = clk_prepare_enable(mdp->clk_main); - if (err < 0) { - dev_err(chip->dev, "Can't enable mdp->clk_main: %pe\n", ERR_PTR(err)); - return err; + if (state->polarity != PWM_POLARITY_NORMAL) + return -EINVAL; + + if (!state->enabled) { + mtk_disp_pwm_update_bits(mdp, DISP_PWM_EN, mdp->data->enable_mask, + 0x0); + if (mdp->enabled) { + clk_disable_unprepare(mdp->clk_mm); + clk_disable_unprepare(mdp->clk_main); + } + mdp->enabled = false; + return 0; } - err = clk_prepare_enable(mdp->clk_mm); - if (err < 0) { - dev_err(chip->dev, "Can't enable mdp->clk_mm: %pe\n", ERR_PTR(err)); - clk_disable_unprepare(mdp->clk_main); - return err; + if (!mdp->enabled) { + err = clk_prepare_enable(mdp->clk_main); + if (err < 0) { + dev_err(chip->dev, "Can't enable mdp->clk_main: %pe\n", + ERR_PTR(err)); + return err; + } + err = clk_prepare_enable(mdp->clk_mm); + if (err < 0) { + dev_err(chip->dev, "Can't enable mdp->clk_mm: %pe\n", + ERR_PTR(err)); + clk_disable_unprepare(mdp->clk_main); + return err; + } } /* @@ -98,20 +116,22 @@ static int mtk_disp_pwm_config(struct pwm_chip *chip, struct pwm_device *pwm, * high_width = (PWM_CLK_RATE * duty_ns) / (10^9 * (clk_div + 1)) */ rate = clk_get_rate(mdp->clk_main); - clk_div = div_u64(rate * period_ns, NSEC_PER_SEC) >> + clk_div = div_u64(rate * state->period, NSEC_PER_SEC) >> PWM_PERIOD_BIT_WIDTH; if (clk_div > PWM_CLKDIV_MAX) { - clk_disable_unprepare(mdp->clk_mm); - clk_disable_unprepare(mdp->clk_main); + if (!mdp->enabled) { + clk_disable_unprepare(mdp->clk_mm); + clk_disable_unprepare(mdp->clk_main); + } return -EINVAL; } div = NSEC_PER_SEC * (clk_div + 1); - period = div64_u64(rate * period_ns, div); + period = div64_u64(rate * state->period, div); if (period > 0) period--; - high_width = div64_u64(rate * duty_ns, div); + high_width = div64_u64(rate * state->duty_cycle, div); value = period | (high_width << PWM_HIGH_WIDTH_SHIFT); mtk_disp_pwm_update_bits(mdp, mdp->data->con0, @@ -140,52 +160,15 @@ static int mtk_disp_pwm_config(struct pwm_chip *chip, struct pwm_device *pwm, mdp->data->con0_sel, mdp->data->con0_sel); } - - clk_disable_unprepare(mdp->clk_mm); - clk_disable_unprepare(mdp->clk_main); - - return 0; -} - -static int mtk_disp_pwm_enable(struct pwm_chip *chip, struct pwm_device *pwm) -{ - struct mtk_disp_pwm *mdp = to_mtk_disp_pwm(chip); - int err; - - err = clk_prepare_enable(mdp->clk_main); - if (err < 0) { - dev_err(chip->dev, "Can't enable mdp->clk_main: %pe\n", ERR_PTR(err)); - return err; - } - - err = clk_prepare_enable(mdp->clk_mm); - if (err < 0) { - dev_err(chip->dev, "Can't enable mdp->clk_mm: %pe\n", ERR_PTR(err)); - clk_disable_unprepare(mdp->clk_main); - return err; - } - mtk_disp_pwm_update_bits(mdp, DISP_PWM_EN, mdp->data->enable_mask, mdp->data->enable_mask); + mdp->enabled = true; return 0; } -static void mtk_disp_pwm_disable(struct pwm_chip *chip, struct pwm_device *pwm) -{ - struct mtk_disp_pwm *mdp = to_mtk_disp_pwm(chip); - - mtk_disp_pwm_update_bits(mdp, DISP_PWM_EN, mdp->data->enable_mask, - 0x0); - - clk_disable_unprepare(mdp->clk_mm); - clk_disable_unprepare(mdp->clk_main); -} - static const struct pwm_ops mtk_disp_pwm_ops = { - .config = mtk_disp_pwm_config, - .enable = mtk_disp_pwm_enable, - .disable = mtk_disp_pwm_disable, + .apply = mtk_disp_pwm_apply, .owner = THIS_MODULE, };